Method for forming hydrogen-passivated semiconductor channels in a three-dimensional memory device

ABSTRACT

A method of forming a three-dimensional memory device includes forming memory stack structures vertically extending through an alternating stack of insulating layers and electrically conductive layers over a substrate, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel laterally surrounded by the memory film. The method also includes forming a stack of a first silicon nitride layer and a second silicon nitride layer over the memory stack structures, such that the first silicon nitride layer has a higher hydrogen-to-nitrogen ratio than the second silicon nitride layer, performing an anneal process at an elevated temperature to diffuse hydrogen from the first silicon nitride layer into the memory stack structures, and removing the first and second silicon nitride layers.

FIELD

The present disclosure relates generally to the field of semiconductordevices and specifically to a method for forming a three-dimensionalmemory device including hydrogen-passivated semiconductor channels, andstructures formed by the method.

BACKGROUND

Recently, ultra high density storage devices employing three-dimensional(3D) memory stack structures have been proposed. Such memory stackstructures can employ an architecture known as Bit Cost Scalable (BiCS)architecture. For example, a 3D NAND stacked memory device can be formedfrom an array of an alternating stack of insulating materials and spacermaterial layers that are formed as electrically conductive layer orreplaced with electrically conductive layers. Memory openings are formedthrough the alternating stack, and are filled with memory stackstructures, each of which includes a vertical stack of memory elementsand a vertical semiconductor channel. A memory-level assembly includingthe alternating stack and the memory stack structures is formed over asubstrate. The electrically conductive layers can function as word linesof a 3D NAND stacked memory device, and bit lines overlying an array ofmemory stack structures can be connected to drain-side ends of thevertical semiconductor channels.

SUMMARY

According to an aspect of the present disclosure, a method of forming athree-dimensional memory device includes forming memory stack structuresvertically extending through an alternating stack of insulating layersand electrically conductive layers over a substrate, such that each ofthe memory stack structures includes a memory film and a verticalsemiconductor channel laterally surrounded by the memory film. Themethod also includes forming a stack of a first silicon nitride layerand a second silicon nitride layer over the memory stack structures,such that the first silicon nitride layer has a higherhydrogen-to-nitrogen ratio than the second silicon nitride layer,performing an anneal process at an elevated temperature to diffusehydrogen from the first silicon nitride layer into the memory stackstructures, and removing the first and second silicon nitride layers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a vertical cross-sectional view of an exemplary structureafter formation of semiconductor devices, lower level dielectric layersincluding a silicon nitride layer, lower metal interconnect structures,and a planar semiconductor material layer on a semiconductor substrateaccording to a first embodiment of the present disclosure.

FIG. 2 is a vertical cross-sectional view of the exemplary structureafter formation of a first-tier alternating stack of first insultinglayers and first spacer material layers according to an embodiment ofthe present disclosure.

FIG. 3 is a vertical cross-sectional view of the exemplary structureafter patterning first-tier staircase regions on the first-tieralternating stack and forming a first-tier retro-stepped dielectricmaterial portion according to an embodiment of the present disclosure.

FIG. 4A is a vertical cross-sectional view of the exemplary structureafter formation of first-tier memory openings and first-tier supportopenings according to an embodiment of the present disclosure.

FIG. 4B is a horizontal cross-sectional view of the exemplary structurealong the horizontal plane B-B′ in FIG. 4A. The zig-zag vertical planeA-A′ corresponds to the plane of the vertical cross-sectional view ofFIG. 4A.

FIG. 5 is a vertical cross-sectional view of the exemplary structureafter formation of sacrificial memory opening fill portions andsacrificial support opening fill portions according to an embodiment ofthe present disclosure.

FIG. 6 is a vertical cross-sectional view of the exemplary structureafter formation of a second-tier alternating stack of second insulatinglayers and second spacer material layers, a second-tier retro-steppeddielectric material portion, and a second insulating cap layer accordingto an embodiment of the present disclosure.

FIG. 7A is a vertical cross-sectional view of the exemplary structureafter formation of inter-tier memory openings and inter-tier supportopenings according to an embodiment of the present disclosure.

FIG. 7B is a horizontal cross-sectional view of the exemplary structurealong the horizontal plane B-B′ in FIG. 7A. The zig-zag vertical planeA-A′ corresponds to the plane of the vertical cross-sectional view ofFIG. 7A.

FIG. 8 is a vertical cross-sectional view of the exemplary structureafter formation of memory stack structures according to an embodiment ofthe present disclosure.

FIGS. 9A-9H are sequential vertical cross-sectional views of aninter-tier memory opening during formation of a pillar channel portion,a memory stack structure, a dielectric core, and a drain regionaccording to an embodiment of the present disclosure.

FIG. 10A is a vertical cross-sectional view of the exemplary structureafter formation of backside contact trenches according to an embodimentof the present disclosure.

FIG. 10B is a horizontal cross-sectional view of the exemplary structurealong the horizontal plane B-B′ in FIG. 10A. The zig-zag vertical planeA-A′ corresponds to the plane of the vertical cross-sectional view ofFIG. 10A.

FIG. 11A is a vertical cross-sectional view of the exemplary structureafter replacement of sacrificial material layers with electricallyconductive layers and formation of insulating spacers and backsidecontact via structures according to an embodiment of the presentdisclosure.

FIG. 11B is a horizontal cross-sectional view of the exemplary structurealong the horizontal plane B-B′ in FIG. 11A. The zig-zag vertical planeA-A′ corresponds to the plane of the vertical cross-sectional view ofFIG. 11A.

FIG. 12A is a vertical cross-sectional view of the exemplary structureafter formation of drain contact via structures and word line contactvia structures according to an embodiment of the present disclosure.

FIG. 12B is a horizontal cross-sectional view of the exemplary structurealong the horizontal plane B-B′ in FIG. 12A. The zig-zag vertical planeA-A′ corresponds to the plane of the vertical cross-sectional view ofFIG. 12A.

FIG. 13A is a vertical cross-sectional view of the exemplary structureafter formation of through-stack contact via structures andthrough-dielectric contact via structures according to an embodiment ofthe present disclosure.

FIG. 13B is a horizontal cross-sectional view of the exemplary structurealong the horizontal plane B-B′ in FIG. 13A. The zig-zag vertical planeA-A′ corresponds to the plane of the vertical cross-sectional view ofFIG. 13A.

FIG. 14 is a vertical cross-sectional view of the exemplary structureafter formation of upper metal line structures according to anembodiment of the present disclosure.

FIG. 15A is a vertical cross-sectional view of the exemplary structureafter formation of a first silicon nitride layer and a second siliconnitride layer according to an embodiment of the present disclosure.

FIG. 15B is a magnified view of a region of the vertical cross-sectionalview of FIG. 15A.

FIG. 15C is a schematic view of a region within a vertical semiconductorchannel in FIG. 15A.

FIG. 16A is a vertical cross-sectional view of the exemplary structureduring an anneal process according to an embodiment of the presentdisclosure.

FIG. 16B is a magnified view of a region of the vertical cross-sectionalview of FIG. 16A.

FIG. 16C is a magnified view of another region of the verticalcross-sectional view of FIG. 16A.

FIG. 16D is a schematic view of a region within a vertical semiconductorchannel in FIG. 16A.

FIG. 17 is a vertical cross-sectional view of the exemplary structureafter removal of the first and second silicon nitride layers accordingto an embodiment of the present disclosure.

FIG. 18 is a vertical cross-sectional view of the exemplary structureafter formation of at least one interconnect level dielectric layerembedding metal interconnect structures and a passivation siliconnitride layer according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

Charge carrier mobility in the vertical semiconductor channels isaffected by dangling bonds that are present at the grain boundaries ofthe vertical semiconductor channels. The present inventors realized thatwhile hydrogen passivation can reduce dangling bonds in the verticalsemiconductor channels of the memory device, hydrogen atoms generallyproduce deleterious effects in underlying driver circuit CMOS devices.

In embodiments of the present disclosure, a method is provided forenhancing charge carrier mobility in the vertical semiconductor channelsof memory stack structures while minimizing introducing hydrogen atomsinto underlying driver circuit CMOS devices. Embodiments of the presentdisclosure provide a method for forming a three-dimensional memorydevice including hydrogen-passivated semiconductor channels using twosilicon nitride layers with different hydrogen concentrations overlyingthe semiconductor channels. The lower silicon nitride layer containsmore hydrogen than the upper silicon nitride layer. The lower siliconnitride layer acts as a hydrogen source for passivating the danglingbonds in the semiconductor channels, while the upper silicon nitridelayer acts as a hydrogen barrier to reduce or prevent diffusion ofhydrogen from the lower silicon nitride layer into the ambient. Theembodiments of the present disclosure can be employed to form varioussemiconductor devices such as three-dimensional monolithic memory arraydevices comprising a plurality of NAND memory strings.

The drawings are not drawn to scale. Multiple instances of an elementmay be duplicated where a single instance of the element is illustrated,unless absence of duplication of elements is expressly described orclearly indicated otherwise. Unless otherwise indicated, a “contact”between elements refers to a direct contact between elements thatprovides an edge or a surface shared by the elements. Ordinals such as“first,” “second,” and “third” are employed merely to identify similarelements, and different ordinals may be employed across thespecification and the claims of the instant disclosure. The samereference numerals refer to the same element or similar element. Unlessotherwise indicated, elements having the same reference numerals arepresumed to have the same composition. As used herein, a first elementlocated “on” a second element can be located on the exterior side of asurface of the second element or on the interior side of the secondelement. As used herein, a first element is located “directly on” asecond element if there exist a physical contact between a surface ofthe first element and a surface of the second element. As used herein,an “in-process” structure or a “transient” structure refers to astructure that is subsequently modified.

As used herein, a “layer” refers to a material portion including aregion having a thickness. A layer may extend over the entirety of anunderlying or overlying structure, or may have an extent less than theextent of an underlying or overlying structure. Further, a layer may bea region of a homogeneous or inhomogeneous continuous structure that hasa thickness less than the thickness of the continuous structure. Forexample, a layer may be located between any pair of horizontal planesbetween or at a top surface and a bottom surface of the continuousstructure. A layer may extend horizontally, vertically, and/or along atapered surface. A substrate may be a layer, may include one or morelayers therein, and/or may have one or more layer thereupon, thereabove,and/or therebelow.

As used herein, a “memory level” or a “memory array level” refers to thelevel corresponding to a general region between a first horizontal plane(i.e., a plane parallel to the top surface of the substrate) includingtopmost surfaces of an array of memory elements and a second horizontalplane including bottommost surfaces of the array of memory elements. Asused herein, a “through-stack” element refers to an element thatvertically extends through a memory level.

As used herein, a “semiconducting material” refers to a material havingelectrical conductivity in the range from 1.0×10⁻⁶ S/cm to 1.0×10⁵ S/cm.As used herein, a “semiconductor material” refers to a material havingelectrical conductivity in the range from 1.0×0⁻⁶ S/cm to 1.0×10⁵ S/cmin the absence of electrical dopants therein, and is capable ofproducing a doped material having electrical conductivity in a rangefrom 1.0 S/cm to 1.0×10⁵ S/cm upon suitable doping with an electricaldopant. As used herein, an “electrical dopant” refers to a p-type dopantthat adds a hole to a valence band within a band structure, or an n-typedopant that adds an electron to a conduction band within a bandstructure. As used herein, a “conductive material” refers to a materialhaving electrical conductivity greater than 1.0×10⁵ S/cm. As usedherein, an “insulating material” or a “dielectric material” refers to amaterial having electrical conductivity less than 1.0×10⁻⁶ S/cm. As usedherein, a “heavily doped semiconductor material” refers to asemiconductor material that is doped with electrical dopant at asufficiently high atomic concentration to become a conductive material,i.e., to have electrical conductivity greater than 1.0×10⁵ S/cm. A“doped semiconductor material” may be a heavily doped semiconductormaterial, or may be a semiconductor material that includes electricaldopants (i.e., p-type dopants and/or n-type dopants) at a concentrationthat provides electrical conductivity in the range from 1.0×10⁻⁶ S/cm to1.0×10⁵ S/cm. An “intrinsic semiconductor material” refers to asemiconductor material that is not doped with electrical dopants. Thus,a semiconductor material may be semiconducting or conductive, and may bean intrinsic semiconductor material or a doped semiconductor material. Adoped semiconductor material can be semiconducting or conductivedepending on the atomic concentration of electrical dopants therein. Asused herein, a “metallic material” refers to a conductive materialincluding at least one metallic element therein. All measurements forelectrical conductivities are made at the standard condition.

A monolithic three-dimensional memory array is one in which multiplememory levels are formed above a single substrate, such as asemiconductor wafer, with no intervening substrates. The term“monolithic” means that layers of each level of the array are directlydeposited on the layers of each underlying level of the array. Incontrast, two dimensional arrays may be formed separately and thenpackaged together to form a non-monolithic memory device. For example,non-monolithic stacked memories have been constructed by forming memorylevels on separate substrates and vertically stacking the memory levels,as described in U.S. Pat. No. 5,915,167 titled “Three-dimensionalStructure Memory.” The substrates may be thinned or removed from thememory levels before bonding, but as the memory levels are initiallyformed over separate substrates, such memories are not true monolithicthree-dimensional memory arrays. The substrate may include integratedcircuits fabricated thereon, such as driver circuits for a memory device

The various three-dimensional memory devices of the present disclosureinclude a monolithic three-dimensional NAND string memory device, andcan be fabricated employing the various embodiments described herein.The monolithic three-dimensional NAND string is located in a monolithic,three-dimensional array of NAND strings located over the substrate. Atleast one memory cell in the first device level of the three-dimensionalarray of NAND strings is located over another memory cell in the seconddevice level of the three-dimensional array of NAND strings.

Referring to FIG. 1, an exemplary structure according to an embodimentof the present disclosure is illustrated. The exemplary structureincludes a semiconductor substrate 8, and semiconductor devices 710formed thereupon. The semiconductor substrate 8 includes a substratesemiconductor layer 9 at least at an upper portion thereof. Shallowtrench isolation structures 720 can be formed in an upper portion of thesubstrate semiconductor layer 9 to provide electrical isolation amongthe semiconductor devices. The semiconductor devices 710 can include,for example, field effect transistors including respective transistoractive regions 742 (i.e., source regions and drain regions), channelregions 746 and gate structures 750. The field effect transistors may bearranged in a CMOS configuration. Each gate structure 750 can include,for example, a gate dielectric 752, a gate electrode 754, a dielectricgate spacer 756 and a gate cap dielectric 758. The semiconductor devicescan include any semiconductor circuitry to support operation of a memorystructure to be subsequently formed, which is typically referred to as adriver circuitry, which is also known as peripheral circuitry. As usedherein, a peripheral circuitry refers to any, each, or all, of word linedecoder circuitry, word line switching circuitry, bit line decodercircuitry, bit line sensing and/or switching circuitry, powersupply/distribution circuitry, data buffer and/or latch, or any othersemiconductor circuitry that can be implemented outside a memory arraystructure for a memory device. For example, the semiconductor devicescan include word line switching devices for electrically biasing wordlines of three-dimensional memory structures to be subsequently formed.

Dielectric material layers are formed over the semiconductor devices,which is herein referred to as lower level dielectric layers 760. Thelower level dielectric layers 760 constitute a dielectric layer stack inwhich each lower level dielectric layer 760 overlies or underlies otherlower level dielectric layers 760. The lower level dielectric layers 760can include, for example, a dielectric liner 762 such as a siliconnitride liner that blocks diffusion of mobile ions and/or applyappropriate stress to underlying structures, at least one firstdielectric material layer 764 that overlies the dielectric liner 762, asilicon nitride diffusion barrier layer 766 (e.g., hydrogen diffusionbarrier) that overlies the dielectric material layer 764, and at leastone second dielectric layer 768. In one embodiment, the silicon nitridediffusion barrier layer 766 can have a hydrogen-to-nitrogen ratio lessthan 0.01, which may be less than 0.005. As used herein, ahydrogen-to-nitrogen ratio in a silicon nitride material refers to theatomic ratio of the hydrogen atoms to the nitrogen atoms. Typicalsilicon nitride has a hydrogen-to-nitrogen ratio of about 0.02. In oneembodiment, the silicon nitride diffusion barrier layer 766 can bedeposited by a low pressure chemical vapor deposition (LPCVD) processemploying dichlorosilane (DCS) and ammonia as reactant gases to providea low hydrogen-to-nitrogen ratio.

The dielectric layer stack including the lower level dielectric layers760 functions as a matrix for lower metal interconnect structures 780that provide electrical wiring among the various nodes of thesemiconductor devices and landing pads for through-stack contact viastructures to be subsequently formed. The lower metal interconnectstructures 780 are embedded within the dielectric layer stack of thelower level dielectric layers 760, and comprise a lower metal linestructure located under and optionally contacting a bottom surface ofthe silicon nitride diffusion barrier layer 766.

For example, the lower metal interconnect structures 780 can be embeddedwithin the at least one first dielectric material layer 764. The atleast one first dielectric material layer 764 may be a plurality ofdielectric material layers in which various elements of the lower metalinterconnect structures 780 are sequentially embedded. Each dielectricmaterial layer among the at least one first dielectric material layer764 may include any of doped silicate glass, undoped silicate glass,organosilicate glass, silicon nitride, silicon oxynitride, anddielectric metal oxides (such as aluminum oxide). In one embodiment, theat least one first dielectric material layer 764 can comprise, orconsist essentially of, dielectric material layers having dielectricconstants that do not exceed the dielectric constant of undoped silicateglass (silicon oxide) of 3.9.

The lower metal interconnect structures 780 can include various devicecontact via structures 782 (e.g., source and drain electrodes whichcontact the respective source and drain nodes of the device or gateelectrode contacts), intermediate lower metal line structures 784, lowermetal via structures 786, and topmost lower metal line structures 788that are configured to function as landing pads for through-stackcontact via structures to be subsequently formed. In this case, the atleast one first dielectric material layer 764 may be a plurality ofdielectric material layers that are formed level by level whileincorporating components of the lower metal interconnect structures 780within each respective level. For example, single damascene processesmay be employed to form the lower metal interconnect structures 780, andeach level of the lower metal via structures 786 may be embedded withina respective via level dielectric material layer and each level of thelower level metal line structures (784, 788) may be embedded within arespective line level dielectric material layer. Alternatively, a dualdamascene process may be employed to form integrated line and viastructures, each of which includes a lower metal line structure and atleast one lower metal via structure.

The topmost lower metal line structures 788 can be formed within atopmost dielectric material layer of the at least one first dielectricmaterial layer 764 (which can be a plurality of dielectric materiallayers). Each of the lower metal interconnect structures 780 can includea metallic nitride liner 78A and a metal fill portion 78B. Each metallicnitride liner 78A can include a conductive metallic nitride materialsuch as TiN, TaN, and/or WN. Each metal fill portion 78B can include anelemental metal (such as Cu, W, Al, Co, Ru) or an intermetallic alloy ofat least two metals. Top surfaces of the topmost lower metal linestructures 788 and the topmost surface of the at least one firstdielectric material layer 764 may be planarized by a planarizationprocess, such as chemical mechanical planarization. In this case, thetop surfaces of the topmost lower metal line structures 788 and thetopmost surface of the at least one first dielectric material layer 764may be within a horizontal plane that is parallel to the top surface ofthe substrate 8.

The silicon nitride diffusion barrier layer 766 can be formed directlyon the top surfaces of the topmost lower metal line structures 788 andthe topmost surface of the at least one first dielectric material layer764. Alternatively, a portion of the first dielectric material layer 764can be located on the top surfaces of the topmost lower metal linestructures 788 below the silicon nitride diffusion barrier layer 766. Inone embodiment, the silicon nitride diffusion barrier layer 766 is asubstantially stoichiometric silicon nitride layer which has acomposition of Si₃N₄. A silicon nitride material formed by thermaldecomposition of a silicon nitride precursor is preferred for thepurpose of blocking hydrogen diffusion. In one embodiment, the siliconnitride diffusion barrier layer 766 can be deposited by a low pressurechemical vapor deposition (LPCVD) employing dichlorosilane (SiH₂Cl₂) andammonia (NH₃) as precursor gases. The temperature of the LPCVD processmay be in a range from 750 degrees Celsius to 825 degrees Celsius,although lesser and greater deposition temperatures can also beemployed. The sum of the partial pressures of dichlorosilane and ammoniamay be in a range from 50 mTorr to 500 mTorr, although lesser andgreater pressures can also be employed. The thickness of the siliconnitride diffusion barrier layer 766 is selected such that the siliconnitride diffusion barrier layer 766 functions as a sufficiently robusthydrogen diffusion barrier for subsequent thermal processes. Forexample, the thickness of the silicon nitride diffusion barrier layer766 can be in a range from 6 nm to 100 nm, although lesser and greaterthicknesses may also be employed.

Generally, semiconductor devices can be formed on a top surface of asubstrate 8 and lower interconnect level dielectric layers (762, 764)embedding lower metal interconnect structures 780 therein are formedover the semiconductor devices. The lower metal interconnect structures780 are electrically connected to a respective one of the semiconductordevices. A silicon nitride diffusion barrier layer 766 may be formedover the lower interconnect level dielectric layer (762, 764). Thesilicon nitride diffusion barrier layer 766 can block diffusion ofhydrogen atoms therethrough during a subsequent anneal process.

The at least one second dielectric material layer 768 may include asingle dielectric material layer or a plurality of dielectric materiallayers. Each dielectric material layer among the at least one seconddielectric material layer 768 may include any of doped silicate glass,undoped silicate glass, and organosilicate glass. In one embodiment, theat least one first second material layer 768 can comprise, or consistessentially of, dielectric material layers having dielectric constantsthat do not exceed the dielectric constant of undoped silicate glass(silicon oxide) of 3.9.

An optional layer of a metallic material and a layer of a semiconductormaterial can be deposited over, or within patterned recesses of, the atleast one second dielectric material layer 768, and is lithographicallypatterned to provide an optional planar conductive material layer 6 anda planar semiconductor material layer 10. The optional planar conductivematerial layer 6, if present, provides a high conductivity conductionpath for electrical current that flows into, or out of, the planarsemiconductor material layer 10. The optional planar conductive materiallayer 6 includes a conductive material such as a metal or a heavilydoped semiconductor material. The optional planar conductive materiallayer 6, for example, may include a tungsten layer having a thickness ina range from 3 nm to 100 nm, although lesser and greater thicknesses canalso be employed. A metal nitride layer (not shown) may be provided as adiffusion barrier layer on top of the planar conductive material layer6. Layer 6 may function as a special source line in the completeddevice. Alternatively, layer 6 may comprise an etch stop layer and maycomprise any suitable conductive, semiconductor or insulating layer.

The planar semiconductor material layer 10 can include horizontalsemiconductor channels and/or source regions for a three-dimensionalarray of memory devices to be subsequently formed. The optional planarconductive material layer 6 can include a metallic compound materialsuch as a conductive metallic nitride (e.g., TiN) and/or a metal (e.g.,W). The thickness of the optional planar conductive material layer 6 maybe in a range from 5 nm to 100 nm, although lesser and greaterthicknesses can also be employed. The planar semiconductor materiallayer 10 includes a polycrystalline semiconductor material such aspolysilicon or a polycrystalline silicon-germanium alloy. The thicknessof the planar semiconductor material layer 10 may be in a range from 30nm to 300 nm, although lesser and greater thicknesses can also beemployed.

The planar semiconductor material layer 10 includes a semiconductormaterial, which can include at least one elemental semiconductormaterial, at least one III-V compound semiconductor material, at leastone II-VI compound semiconductor material, at least one organicsemiconductor material, and/or other semiconductor materials known inthe art. In one embodiment, the planar semiconductor material layer 10can include a polycrystalline semiconductor material (such aspolysilicon), or an amorphous semiconductor material (such as amorphoussilicon) that is converted into a polycrystalline semiconductor materialin a subsequent processing step (such as an anneal step). The planarsemiconductor material layer 10 can be formed directly above a subset ofthe semiconductor devices on the semiconductor substrate 8 (e.g.,silicon wafer). As used herein, a first element is located “directlyabove” a second element if the first element is located above ahorizontal plane including a topmost surface of the second element andan area of the first element and an area of the second element has anareal overlap in a plan view (i.e., along a vertical plane or directionperpendicular to the top surface of the substrate 9). In one embodiment,the planar semiconductor material layer 10 or portions thereof can bedoped with electrical dopants, which may be p-type dopants or n-typedopants. The conductivity type of the dopants in the planarsemiconductor material layer 10 is herein referred to as a firstconductivity type.

The optional planar conductive material layer 6 and the planarsemiconductor material layer 10 may be patterned to provide openings inareas in which through-stack contact via structures andthrough-dielectric contact via structures are to be subsequently formed.In one embodiment, the openings in the optional planar conductivematerial layer 6 and the planar semiconductor material layer 10 can beformed within the area of a memory array region 100, in which athree-dimensional memory array including memory stack structures is tobe subsequently formed. Further, additional openings in the optionalplanar conductive material layer 6 and the planar semiconductor materiallayer 10 can be formed within the area of a word line contact region 200in which contact via structures contacting word line electricallyconductive layers are to be subsequently formed.

The region of the semiconductor devices 710 and the combination of thelower level dielectric layers 760 and the lower metal interconnectstructures 780 is herein referred to an underlying peripheral deviceregion 700, which is located underneath a memory-level assembly to besubsequently formed and includes peripheral devices for the memory-levelassembly. The lower metal interconnect structures 780 are embedded inthe lower level dielectric layers 760.

The lower metal interconnect structures 780 can be electrically shortedto active nodes (e.g., transistor active regions 742 or gate electrodes750) of the semiconductor devices 710 (e.g., CMOS devices), and arelocated at the level of the lower level dielectric layers 760. Only asubset of the active nodes is illustrated in FIG. 1 for clarity.Through-stack contact via structures (not shown in FIG. 1) can besubsequently formed directly on the lower metal interconnect structures780 to provide electrical connection to memory devices to besubsequently formed. In one embodiment, the pattern of the lower metalinterconnect structures 780 can be selected such that the topmost lowermetal line structures 788 (which are a subset of the lower metalinterconnect structures 780 located at the topmost portion of the lowermetal interconnect structures 780) can provide landing pad structuresfor the through-stack contact via structures to be subsequently formed.

Referring to FIG. 2, an alternating stack of first material layers andsecond material layers is subsequently formed. Each first material layercan include a first material, and each second material layer can includea second material that is different from the first material. In case atleast another alternating stack of material layers is subsequentlyformed over the alternating stack of the first material layers and thesecond material layers, the alternating stack is herein referred to as afirst-tier alternating stack. The level of the first-tier alternatingstack is herein referred to as a first-tier level, and the level of thealternating stack to be subsequently formed immediately above thefirst-tier level is herein referred to as a second-tier level, etc.

The first-tier alternating stack can include first insulting layers 132as the first material layers, and first spacer material layers as thesecond material layers. In one embodiment, the first spacer materiallayers can be sacrificial material layers that are subsequently replacedwith electrically conductive layers. In another embodiment, the firstspacer material layers can be electrically conductive layers that arenot subsequently replaced with other layers. While the presentdisclosure is described employing embodiments in which sacrificialmaterial layers are replaced with electrically conductive layers,embodiments in which the spacer material layers are formed aselectrically conductive layers (thereby obviating the need to performreplacement processes) are expressly contemplated herein.

In one embodiment, the first material layers and the second materiallayers can be first insulating layers 132 and first sacrificial materiallayers 142, respectively. In one embodiment, each first insulating layer132 can include a first insulating material, and each first sacrificialmaterial layer 142 can include a first sacrificial material. Analternating plurality of first insulating layers 132 and firstsacrificial material layers 142 is formed over the planar semiconductormaterial layer 10. As used herein, a “sacrificial material” refers to amaterial that is removed during a subsequent processing step.

As used herein, an alternating stack of first elements and secondelements refers to a structure in which instances of the first elementsand instances of the second elements alternate. Each instance of thefirst elements that is not an end element of the alternating pluralityis adjoined by two instances of the second elements on both sides, andeach instance of the second elements that is not an end element of thealternating plurality is adjoined by two instances of the first elementson both ends. The first elements may have the same thicknessthereamongst, or may have different thicknesses. The second elements mayhave the same thickness thereamongst, or may have different thicknesses.The alternating plurality of first material layers and second materiallayers may begin with an instance of the first material layers or withan instance of the second material layers, and may end with an instanceof the first material layers or with an instance of the second materiallayers. In one embodiment, an instance of the first elements and aninstance of the second elements may form a unit that is repeated withperiodicity within the alternating plurality.

The first-tier alternating stack (132, 142) can include first insulatinglayers 132 composed of the first material, and first sacrificialmaterial layers 142 composed of the second material, which is differentfrom the first material. The first material of the first insulatinglayers 132 can be at least one insulating material. Insulating materialsthat can be employed for the first insulating layers 132 include, butare not limited to silicon oxide (including doped or undoped silicateglass), silicon nitride, silicon oxynitride, organosilicate glass (OSG),spin-on dielectric materials, dielectric metal oxides that are commonlyknown as high dielectric constant (high-k) dielectric oxides (e.g.,aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectricmetal oxynitrides and silicates thereof, and organic insulatingmaterials. In one embodiment, the first material of the first insulatinglayers 132 can be silicon oxide.

The second material of the first sacrificial material layers 142 is asacrificial material that can be removed selective to the first materialof the first insulating layers 132. As used herein, a removal of a firstmaterial is “selective to” a second material if the removal processremoves the first material at a rate that is at least twice the rate ofremoval of the second material. The ratio of the rate of removal of thefirst material to the rate of removal of the second material is hereinreferred to as a “selectivity” of the removal process for the firstmaterial with respect to the second material.

The first sacrificial material layers 142 may comprise an insulatingmaterial, a semiconductor material, or a conductive material. The secondmaterial of the first sacrificial material layers 142 can besubsequently replaced with electrically conductive electrodes which canfunction, for example, as control gate electrodes of a vertical NANDdevice. In one embodiment, the first sacrificial material layers 142 canbe material layers that comprise silicon nitride.

In one embodiment, the first insulating layers 132 can include siliconoxide, and sacrificial material layers can include silicon nitridesacrificial material layers. The first material of the first insulatinglayers 132 can be deposited, for example, by chemical vapor deposition(CVD). For example, if silicon oxide is employed for the firstinsulating layers 132, tetraethylorthosilicate (TEOS) can be employed asthe precursor material for the CVD process. The second material of thefirst sacrificial material layers 142 can be formed, for example, CVD oratomic layer deposition (ALD).

The thicknesses of the first insulating layers 132 and the firstsacrificial material layers 142 can be in a range from 20 nm to 50 nm,although lesser and greater thicknesses can be employed for each firstinsulating layer 132 and for each first sacrificial material layer 142.The number of repetitions of the pairs of a first insulating layer 132and a first sacrificial material layer 142 can be in a range from 2 to1,024, and typically from 8 to 256, although a greater number ofrepetitions can also be employed. In one embodiment, each firstsacrificial material layer 142 in the first-tier alternating stack (132,142) can have a uniform thickness that is substantially invariant withineach respective first sacrificial material layer 142.

A first insulating cap layer 170 is subsequently formed over the stack(132, 142). The first insulating cap layer 170 includes a dielectricmaterial, which can be any dielectric material that can be employed forthe first insulating layers 132. In one embodiment, the first insulatingcap layer 170 includes the same dielectric material as the firstinsulating layers 132. The thickness of the insulating cap layer 170 canbe in a range from 20 nm to 300 nm, although lesser and greaterthicknesses can also be employed.

Referring to FIG. 3, the first insulating cap layer 170 and thefirst-tier alternating stack (132, 142) can be patterned to form firststepped surfaces in the word line contact region 200. The word line wordline contact region 200 can include a respective first stepped area inwhich the first stepped surfaces are formed, and a second stepped areain which additional stepped surfaces are to be subsequently formed in asecond-tier structure (to be subsequently formed over a first-tierstructure) and/or additional tier structures. The first stepped surfacescan be formed, for example, by forming a mask layer with an openingtherein, etching a cavity within the levels of the first insulating caplayer 170, and iteratively expanding the etched area and verticallyrecessing the cavity by etching each pair of a first insulating layer132 and a first sacrificial material layer 142 located directlyunderneath the bottom surface of the etched cavity within the etchedarea. A dielectric material can be deposited to fill the first steppedcavity to form a first-tier retro-stepped dielectric material portion165. As used herein, a “retro-stepped” element refers to an element thathas stepped surfaces and a horizontal cross-sectional area thatincreases monotonically as a function of a vertical distance from a topsurface of a substrate on which the element is present. The first-tieralternating stack (132, 142) and the first-tier retro-stepped dielectricmaterial portion 165 collectively constitute a first-tier structure,which is an in-process structure that is subsequently modified.

Referring to FIGS. 4A and 4B, an inter-tier dielectric layer 180 may beoptionally deposited over the first-tier structure (132, 142, 165, 170).The inter-tier dielectric layer 180 includes a dielectric material suchas silicon oxide. The thickness of the inter-tier dielectric layer 180can be in a range from 30 nm to 300 nm, although lesser and greaterthicknesses can also be employed. Locations of steps S in the first-tieralternating stack (132, 142) are illustrated as dotted lines.

First-tier memory openings 149 and first-tier support openings 119 canbe formed. The first-tier memory openings 149 and the first-tier supportopenings 119 extend through the first-tier alternating stack (132, 142)at least to a top surface of the planar semiconductor material layer 10.The first-tier memory openings 149 can be formed in the memory arrayregion 100 at locations at which memory stack structures includingvertical stacks of memory elements are to be subsequently formed. Thefirst-tier support openings 119 can be formed in the word line word linecontact region 200. For example, a lithographic material stack (notshown) including at least a photoresist layer can be formed over thefirst insulating cap layer 170 (and the optional inter-tier dielectriclayer 180, if present), and can be lithographically patterned to formopenings within the lithographic material stack. The pattern in thelithographic material stack can be transferred through the firstinsulating cap layer 170 (and the optional inter-tier dielectric layer180), and through the entirety of the first-tier alternating stack (132,142) by at least one anisotropic etch that employs the patternedlithographic material stack as an etch mask. Portions of the firstinsulating cap layer 170 (and the optional inter-tier dielectric layer180), and the first-tier alternating stack (132, 142) underlying theopenings in the patterned lithographic material stack are etched to formthe first-tier memory openings 149 and the first-tier support openings119. In other words, the transfer of the pattern in the patternedlithographic material stack through the first insulating cap layer 170and the first-tier alternating stack (132, 142) forms the first-tiermemory openings 149 and the first-tier support openings 119.

In one embodiment, the chemistry of the anisotropic etch processemployed to etch through the materials of the first-tier alternatingstack (132, 142) can alternate to optimize etching of the first andsecond materials in the first-tier alternating stack (132, 142). Theanisotropic etch can be, for example, a series of reactive ion etches ora single etch (e.g., CF₄/O₂/Ar etch). The sidewalls of the first-tiermemory openings 149 and the support openings 119 can be substantiallyvertical, or can be tapered. Subsequently, the patterned lithographicmaterial stack can be subsequently removed, for example, by ashing.

Optionally, the portions of the first-tier memory openings 149 and thefirst-tier support openings 119 at the level of the inter-tierdielectric layer 180 can be laterally expanded by an isotropic etch. Forexample, if the inter-tier dielectric layer 180 comprises a dielectricmaterial (such as borosilicate glass) having a greater etch rate thanthe first insulating layers 132 (that can include undoped silicateglass), an isotropic etch (such as a wet etch employing HF) can beemployed to expand the lateral dimensions of the first-tier memoryopenings at the level of the inter-tier dielectric layer 180. Theportions of the first-tier memory openings 149 (and the first-tiersupport openings 119) located at the level of the inter-tier dielectriclayer 180 may be optionally widened to provide a larger landing pad forsecond-tier memory openings to be subsequently formed through asecond-tier alternating stack (to be subsequently formed prior toformation of the second-tier memory openings).

Referring to FIG. 5, sacrificial memory opening fill portions 148 can beformed in the first-tier memory openings 149, and sacrificial supportopening fill portions 118 can be formed in the first-tier supportopenings 119. For example, a sacrificial fill material layer isdeposited in the first-tier memory openings 149 and the first-tiersupport openings 119. The sacrificial fill material layer includes asacrificial material which can be subsequently removed selective to thematerials of the first insulator layers 132 and the first sacrificialmaterial layers 142. In one embodiment, the sacrificial fill materiallayer can include germanium, a silicon-germanium alloy, carbon,borosilicate glass (which provides higher etch rate relative to undopedsilicate glass), porous or non-porous organosilicate glass, organicpolymer, inorganic polymer or amorphous silicon (if semiconductormaterial layer 10 is a polysilicon layer and/or if a sacrificialdielectric liner is formed in the openings first). Optionally, a thinetch stop layer (such as a silicon oxide layer having a thickness in arange from 1 nm to 3 nm) may be employed prior to depositing thesacrificial fill material layer. The sacrificial fill material layer maybe formed by a non-conformal deposition or a conformal depositionmethod.

Portions of the deposited sacrificial material can be removed from abovethe first insulating cap layer 170 (and the optional inter-tierdielectric layer 180, if present). For example, the sacrificial fillmaterial layer can be recessed to a top surface of the first insulatingcap layer 170 (and the optional inter-tier dielectric layer 180)employing a planarization process. The planarization process can includea recess etch, chemical mechanical planarization (CMP), or a combinationthereof. The top surface of the first insulating layer 170 (andoptionally layer 180 if present) can be employed as an etch stop layeror a planarization stop layer. Each remaining portion of the sacrificialmaterial in a first-tier memory opening 149 constitutes a sacrificialmemory opening fill portion 148. Each remaining portion of thesacrificial material in a first-tier support opening 119 constitutes asacrificial support opening fill portion 118. The top surfaces of thesacrificial memory opening fill portions 148 and the sacrificial supportopening fill portions 118 can be coplanar with the top surface of theinter-tier dielectric layer 180 (or the first insulating cap layer 170if the inter-tier dielectric layer 180 is not present). The sacrificialmemory opening fill portion 148 and the sacrificial support opening fillportions 118 may, or may not, include cavities therein.

Referring to FIG. 6, a second-tier structure can be formed over thefirst-tier structure (132, 142, 170, 148, 118). The second-tierstructure can include an additional alternating stack of insulatinglayers and spacer material layers, which can be sacrificial materiallayers. For example, a second alternating stack (232, 242) of materiallayers can be subsequently formed on the top surface of the firstalternating stack (132, 142). The second stack (232, 242) includes analternating plurality of third material layers and fourth materiallayers. Each third material layer can include a third material, and eachfourth material layer can include a fourth material that is differentfrom the third material. In one embodiment, the third material can bethe same as the first material of the first insulating layer 132, andthe fourth material can be the same as the second material of the firstsacrificial material layers 142.

In one embodiment, the third material layers can be second insulatinglayers 232 and the fourth material layers can be second spacer materiallayers that provide vertical spacing between each vertically neighboringpair of the second insulating layers 232. In one embodiment, the thirdmaterial layers and the fourth material layers can be second insulatinglayers 232 and second sacrificial material layers 242, respectively. Thethird material of the second insulating layers 232 may be at least oneinsulating material. The fourth material of the second sacrificialmaterial layers 242 may be a sacrificial material that can be removedselective to the third material of the second insulating layers 232. Thesecond sacrificial material layers 242 may comprise an insulatingmaterial, a semiconductor material, or a conductive material. The fourthmaterial of the second sacrificial material layers 242 can besubsequently replaced with electrically conductive electrodes which canfunction, for example, as control gate electrodes of a vertical NANDdevice.

In one embodiment, each second insulating layer 232 can include a secondinsulating material, and each second sacrificial material layer 242 caninclude a second sacrificial material. In this case, the second stack(232, 242) can include an alternating plurality of second insulatinglayers 232 and second sacrificial material layers 242. The thirdmaterial of the second insulating layers 232 can be deposited, forexample, by chemical vapor deposition (CVD). The fourth material of thesecond sacrificial material layers 242 can be formed, for example, CVDor atomic layer deposition (ALD).

The third material of the second insulating layers 232 can be at leastone insulating material. Insulating materials that can be employed forthe second insulating layers 232 can be any material that can beemployed for the first insulating layers 132. The fourth material of thesecond sacrificial material layers 242 is a sacrificial material thatcan be removed selective to the third material of the second insulatinglayers 232. Sacrificial materials that can be employed for the secondsacrificial material layers 242 can be any material that can be employedfor the first sacrificial material layers 142. In one embodiment, thesecond insulating material can be the same as the first insulatingmaterial, and the second sacrificial material can be the same as thefirst sacrificial material.

The thicknesses of the second insulating layers 232 and the secondsacrificial material layers 242 can be in a range from 20 nm to 50 nm,although lesser and greater thicknesses can be employed for each secondinsulating layer 232 and for each second sacrificial material layer 242.The number of repetitions of the pairs of a second insulating layer 232and a second sacrificial material layer 242 can be in a range from 2 to1,024, and typically from 8 to 256, although a greater number ofrepetitions can also be employed. In one embodiment, each secondsacrificial material layer 242 in the second stack (232, 242) can have auniform thickness that is substantially invariant within each respectivesecond sacrificial material layer 242.

Second stepped surfaces in the second stepped area can be formed in theword line word line contact region 200 employing a same set ofprocessing steps as the processing steps employed to form the firststepped surfaces in the first stepped area with suitable adjustment tothe pattern of at least one masking layer. A second-tier retro-steppeddielectric material portion 265 can be formed over the second steppedsurfaces in the word line word line contact region 200.

A second insulating cap layer 270 can be subsequently formed over thesecond alternating stack (232, 242). The second insulating cap layer 270includes a dielectric material that is different from the material ofthe second sacrificial material layers 242. In one embodiment, thesecond insulating cap layer 270 can include silicon oxide. In oneembodiment, the first and second sacrificial material layers (142, 242)can comprise silicon nitride.

Generally speaking, at least one alternating stack of insulating layers(132, 232) and spacer material layers (such as sacrificial materiallayers (142, 242)) can be formed over the planar semiconductor materiallayer 10, and at least one retro-stepped dielectric material portion(165, 265) can be formed over the staircase regions on the at least onealternating stack (132, 142, 232, 242).

Optionally, drain-select-level shallow trench isolation structures 72can be formed through a subset of layers in an upper portion of thesecond-tier alternating stack (232, 242). The second sacrificialmaterial layers 242 that are cut by the select-drain-level shallowtrench isolation structures 72 correspond to the levels in whichdrain-select-level electrically conductive layers are subsequentlyformed. The drain-select-level shallow trench isolation structures 72include a dielectric material such as silicon oxide.

Referring to FIGS. 7A and 7B, second-tier memory openings 249 andsecond-tier support openings 219 extending through the second-tierstructure (232, 242, 270, 265) are formed in areas overlying thesacrificial memory opening fill portions 148. A photoresist layer can beapplied over the second-tier structure (232, 242, 270, 265), and can belithographically patterned to form a same pattern as the pattern of thesacrificial memory opening fill portions 148 and the sacrificial supportopening fill portions 118, i.e., the pattern of the first-tier memoryopenings 149 and the first-tier support openings 119. Thus, thelithographic mask employed to pattern the first-tier memory openings 149and the first-tier support openings 119 can be employed to pattern thesecond-tier memory openings 249 and the second-tier support openings219. An anisotropic etch can be performed to transfer the pattern of thelithographically patterned photoresist layer through the second-tierstructure (232, 242, 270, 265). In one embodiment, the chemistry of theanisotropic etch process employed to etch through the materials of thesecond-tier alternating stack (232, 242) can alternate to optimizeetching of the alternating material layers in the second-tieralternating stack (232, 242). The anisotropic etch can be, for example,a series of reactive ion etches. The patterned lithographic materialstack can be removed, for example, by ashing after the anisotropic etchprocess.

A top surface of an underlying sacrificial memory opening fill portion148 can be physically exposed at the bottom of each second-tier memoryopening 249. A top surface of an underlying sacrificial support openingfill portion 118 can be physically exposed at the bottom of eachsecond-tier support opening 219. After the top surfaces of thesacrificial memory opening fill portions 148 and the sacrificial supportopening fill portions 118 are physically exposed, an etch process can beperformed, which removes the sacrificial material of the sacrificialmemory opening fill portions 148 and the sacrificial support openingfill portions 118 selective to the materials of the second-tieralternating stack (232, 242) and the first-tier alternating stack (132,142) (e.g., C₄F₈/O₂/Ar etch).

Upon removal of the sacrificial memory opening fill portions 148, eachvertically adjoining pair of a second-tier memory opening 249 and afirst-tier memory opening 149 forms a continuous cavity that extendsthrough the first-tier alternating stack (132, 142) and the second-tieralternating stack (232, 242). Likewise, upon removal of the sacrificialsupport opening fill portions 118, each vertically adjoining pair of asecond-tier support opening 219 and a first-tier support opening 119forms a continuous cavity that extends through the first-tieralternating stack (132, 142) and the second-tier alternating stack (232,242). The continuous cavities are herein referred to as memory openings(or inter-tier memory openings) and support openings (or inter-tiersupport openings), respectively. A top surface of the planarsemiconductor material layer 10 can be physically exposed at the bottomof each memory opening and at the bottom of each support openings.Locations of steps S in the first-tier alternating stack (132, 142) andthe second-tier alternating stack (232, 242) are illustrated as dottedlines.

Referring to FIG. 8, memory opening fill structures 58 are formed withineach memory opening, and support pillar structures 20 are formed withineach support opening. The memory opening fill structures 58 and thesupport pillar structures 20 can include a same set of components, andcan be formed simultaneously.

FIGS. 9A-9H provide sequential cross-sectional views of a memory opening49 or a support opening (119, 219) during formation of a memory openingfill structure 58 or a support pillar structure 20. While a structuralchange in a memory opening 49 is illustrated in FIGS. 9A-9H, it isunderstood that the same structural change occurs in each memoryopenings 49 and in each of the support openings (119, 219) during thesame set of processing steps.

Referring to FIG. 9A, a memory opening 49 in the exemplary devicestructure of FIG. 12 is illustrated. The memory opening 49 extendsthrough the first-tier structure and the second-tier structure.Likewise, each support opening (119, 219) extends through the first-tierstructure and the second-tier structure.

Referring to FIG. 9B, an optional pedestal channel portion (e.g., anepitaxial pedestal) 11 can be formed at the bottom portion of eachmemory opening 49 and each support openings (119, 219), for example, bya selective semiconductor deposition process. In one embodiment, thepedestal channel portion 11 can be doped with electrical dopants of thesame conductivity type as the planar semiconductor material layer 10. Inone embodiment, at least one source select gate electrode can besubsequently formed by replacing each sacrificial material layer 42located below the horizontal plane including the top surfaces of thepedestal channel portions 11 with a respective conductive materiallayer. A cavity 49′ is present in the unfilled portion of the memoryopening 49 (or of the support opening) above the pedestal channelportion 11. In one embodiment, the pedestal channel portion 11 cancomprise single crystalline silicon. In one embodiment, the pedestalchannel portion 11 can have a doping of the same as the conductivitytype of the planar semiconductor material layer 10.

Referring to FIG. 9C, a stack of layers including a blocking dielectriclayer 52, a charge storage layer 54, a tunneling dielectric layer 56,and an optional first semiconductor channel layer 601 can besequentially deposited in the memory openings 49.

The blocking dielectric layer 52 can include a single dielectricmaterial layer or a stack of a plurality of dielectric material layers.In one embodiment, the blocking dielectric layer can include adielectric metal oxide layer consisting essentially of a dielectricmetal oxide. As used herein, a dielectric metal oxide refers to adielectric material that includes at least one metallic element and atleast oxygen. The dielectric metal oxide may consist essentially of theat least one metallic element and oxygen, or may consist essentially ofthe at least one metallic element, oxygen, and at least one non-metallicelement such as nitrogen. In one embodiment, the blocking dielectriclayer 52 can include a dielectric metal oxide having a dielectricconstant greater than 7.9, i.e., having a dielectric constant greaterthan the dielectric constant of silicon nitride.

Non-limiting examples of dielectric metal oxides include aluminum oxide(A1 ₂O₃), hafnium oxide (HfO₂), lanthanum oxide (LaO₂), yttrium oxide(Y₂O₃), tantalum oxide (Ta₂O₅), silicates thereof, nitrogen-dopedcompounds thereof, alloys thereof, and stacks thereof. The dielectricmetal oxide layer can be deposited, for example, by chemical vapordeposition (CVD), atomic layer deposition (ALD), pulsed laser deposition(PLD), liquid source misted chemical deposition, or a combinationthereof. The thickness of the dielectric metal oxide layer can be in arange from 1 nm to 20 nm, although lesser and greater thicknesses canalso be employed. The dielectric metal oxide layer can subsequentlyfunction as a dielectric material portion that blocks leakage of storedelectrical charges to control gate electrodes. In one embodiment, theblocking dielectric layer 52 includes aluminum oxide. In one embodiment,the blocking dielectric layer 52 can include multiple dielectric metaloxide layers having different material compositions.

Alternatively or additionally, the blocking dielectric layer 52 caninclude a dielectric semiconductor compound such as silicon oxide,silicon oxynitride, silicon nitride, or a combination thereof. In oneembodiment, the blocking dielectric layer 52 can include silicon oxide.In this case, the dielectric semiconductor compound of the blockingdielectric layer 52 can be formed by a conformal deposition method suchas low pressure chemical vapor deposition, atomic layer deposition, or acombination thereof. The thickness of the dielectric semiconductorcompound can be in a range from 1 nm to 20 nm, although lesser andgreater thicknesses can also be employed. Alternatively, the blockingdielectric layer 52 can be omitted, and a backside blocking dielectriclayer can be formed after formation of backside recesses on surfaces ofmemory films to be subsequently formed.

Subsequently, the charge storage layer 54 can be formed. In oneembodiment, the charge storage layer 54 can be a continuous layer orpatterned discrete portions of a charge trapping material including adielectric charge trapping material, which can be, for example, siliconnitride. Alternatively, the charge storage layer 54 can include acontinuous layer or patterned discrete portions of a conductive materialsuch as doped polysilicon or a metallic material that is patterned intomultiple electrically isolated portions (e.g., floating gates), forexample, by being formed within lateral recesses into sacrificialmaterial layers (142, 242). In one embodiment, the charge storage layer54 includes a silicon nitride layer. In one embodiment, the sacrificialmaterial layers (142, 242) and the insulating layers (132, 232) can havevertically coincident sidewalls, and the charge storage layer 54 can beformed as a single continuous layer.

In another embodiment, the sacrificial material layers (142, 242) can belaterally recessed with respect to the sidewalls of the insulatinglayers (132, 232), and a combination of a deposition process and ananisotropic etch process can be employed to form the charge storagelayer 54 as a plurality of memory material portions that are verticallyspaced apart. While the present disclosure is described employing anembodiment in which the charge storage layer 54 is a single continuouslayer, embodiments are expressly contemplated herein in which the chargestorage layer 54 is replaced with a plurality of memory materialportions (which can be charge trapping material portions or electricallyisolated conductive material portions) that are vertically spaced apart.

The charge storage layer 54 can be formed as a single charge storagelayer of homogeneous composition, or can include a stack of multiplecharge storage layers. The multiple charge storage layers, if employed,can comprise a plurality of spaced-apart floating gate material layersthat contain conductive materials (e.g., metal such as tungsten,molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof,or a metal silicide such as tungsten silicide, molybdenum silicide,tantalum silicide, titanium silicide, nickel silicide, cobalt silicide,or a combination thereof) and/or semiconductor materials (e.g.,polycrystalline or amorphous semiconductor material including at leastone elemental semiconductor element or at least one compoundsemiconductor material). Alternatively or additionally, the chargestorage layer 54 may comprise an insulating charge trapping material,such as one or more silicon nitride segments. Alternatively, the chargestorage layer 54 may comprise conductive nanoparticles such as metalnanoparticles, which can be, for example, ruthenium nanoparticles. Thecharge storage layer 54 can be formed, for example, by chemical vapordeposition (CVD), atomic layer deposition (ALD), physical vapordeposition (PVD), or any suitable deposition technique for storingelectrical charges therein. The thickness of the charge storage layer 54can be in a range from 2 nm to 20 nm, although lesser and greaterthicknesses can also be employed.

The tunneling dielectric layer 56 includes a dielectric material throughwhich charge tunneling can be performed under suitable electrical biasconditions. The charge tunneling may be performed through hot-carrierinjection or by Fowler-Nordheim tunneling induced charge transferdepending on the mode of operation of the monolithic three-dimensionalNAND string memory device to be formed. The tunneling dielectric layer56 can include silicon oxide, silicon nitride, silicon oxynitride,dielectric metal oxides (such as aluminum oxide and hafnium oxide),dielectric metal oxynitride, dielectric metal silicates, alloys thereof,and/or combinations thereof. In one embodiment, the tunneling dielectriclayer 56 can include a stack of a first silicon oxide layer, a siliconoxynitride layer, and a second silicon oxide layer, which is commonlyknown as an ONO stack. In one embodiment, the tunneling dielectric layer56 can include a silicon oxide layer that is substantially free ofcarbon or a silicon oxynitride layer that is substantially free ofcarbon. The thickness of the tunneling dielectric layer 56 can be in arange from 2 nm to 20 nm, although lesser and greater thicknesses canalso be employed.

The optional first semiconductor channel layer 601 includes asemiconductor material such as at least one elemental semiconductormaterial, at least one III-V compound semiconductor material, at leastone II-VI compound semiconductor material, at least one organicsemiconductor material, or other semiconductor materials known in theart. In one embodiment, the first semiconductor channel layer 601includes amorphous silicon or polysilicon. The first semiconductorchannel layer 601 can be formed by a conformal deposition method such aslow pressure chemical vapor deposition (LPCVD). The thickness of thefirst semiconductor channel layer 601 can be in a range from 2 nm to 10nm, although lesser and greater thicknesses can also be employed. Acavity 49′ is formed in the volume of each memory opening 49 that is notfilled with the deposited material layers (52, 54, 56, 601).

Referring to FIG. 9D, the optional first semiconductor channel layer601, the tunneling dielectric layer 56, the charge storage layer 54, theblocking dielectric layer 52 are sequentially anisotropically etchedemploying at least one anisotropic etch process. The portions of thefirst semiconductor channel layer 601, the tunneling dielectric layer56, the charge storage layer 54, and the blocking dielectric layer 52located above the top surface of the second insulating cap layer 270 canbe removed by the at least one anisotropic etch process. Further, thehorizontal portions of the first semiconductor channel layer 601, thetunneling dielectric layer 56, the charge storage layer 54, and theblocking dielectric layer 52 at a bottom of each cavity 49′ can beremoved to form openings in remaining portions thereof. Each of thefirst semiconductor channel layer 601, the tunneling dielectric layer56, the charge storage layer 54, and the blocking dielectric layer 52can be etched by a respective anisotropic etch process employing arespective etch chemistry, which may, or may not, be the same for thevarious material layers.

Each remaining portion of the first semiconductor channel layer 601 canhave a tubular configuration. The charge storage layer 54 can comprise acharge trapping material or a floating gate material. In one embodiment,each charge storage layer 54 can include a vertical stack of chargestorage regions that store electrical charges upon programming. In oneembodiment, the charge storage layer 54 can be a charge storage layer inwhich each portion adjacent to the sacrificial material layers (142,242) constitutes a charge storage region.

A surface of the pedestal channel portion 11 (or a surface of the planarsemiconductor material layer 10 in case the pedestal channel portions 11are not employed) can be physically exposed underneath the openingthrough the first semiconductor channel layer 601, the tunnelingdielectric layer 56, the charge storage layer 54, and the blockingdielectric layer 52. Optionally, the physically exposed semiconductorsurface at the bottom of each cavity 49′ can be vertically recessed sothat the recessed semiconductor surface underneath the cavity 49′ isvertically offset from the topmost surface of the pedestal channelportion 11 (or of the semiconductor material layer 10 in case pedestalchannel portions 11 are not employed) by a recess distance. A tunnelingdielectric layer 56 is located over the charge storage layer 54. A setof a blocking dielectric layer 52, a charge storage layer 54, and atunneling dielectric layer 56 in a memory opening 49 constitutes amemory film 50, which includes a plurality of charge storage regions (asembodied as the charge storage layer 54) that are insulated fromsurrounding materials by the blocking dielectric layer 52 and thetunneling dielectric layer 56. In one embodiment, the firstsemiconductor channel layer 601, the tunneling dielectric layer 56, thecharge storage layer 54, and the blocking dielectric layer 52 can havevertically coincident sidewalls.

Referring to FIG. 9E, a second semiconductor channel layer 602 can bedeposited directly on the semiconductor surface of the pedestal channelportion 11 or the semiconductor material layer 10 if the pedestalchannel portion 11 is omitted, and directly on the first semiconductorchannel layer 601. The second semiconductor channel layer 602 includes asemiconductor material such as at least one elemental semiconductormaterial, at least one III-V compound semiconductor material, at leastone II-VI compound semiconductor material, at least one organicsemiconductor material, or other semiconductor materials known in theart. In one embodiment, the second semiconductor channel layer 602includes amorphous silicon or polysilicon. The second semiconductorchannel layer 602 can be formed by a conformal deposition method such aslow pressure chemical vapor deposition (LPCVD). The thickness of thesecond semiconductor channel layer 602 can be in a range from 2 nm to 10nm, although lesser and greater thicknesses can also be employed. Thesecond semiconductor channel layer 602 may partially fill the cavity 49′in each memory opening, or may fully fill the cavity in each memoryopening.

The materials of the first semiconductor channel layer 601 and thesecond semiconductor channel layer 602 are collectively referred to as asemiconductor channel material. In other words, the semiconductorchannel material is a set of all semiconductor material in the firstsemiconductor channel layer 601 and the second semiconductor channellayer 602.

Referring to FIG. 9F, in case the cavity 49′ in each memory opening isnot completely filled by the second semiconductor channel layer 602, adielectric core layer 62L can be deposited in the cavity 49′ to fill anyremaining portion of the cavity 49′ within each memory opening. Thedielectric core layer 62L includes a dielectric material such as siliconoxide or organosilicate glass. The dielectric core layer 62L can bedeposited by a conformal deposition method such as low pressure chemicalvapor deposition (LPCVD), or by a self-planarizing deposition processsuch as spin coating.

Referring to FIG. 9G, the horizontal portion of the dielectric corelayer 62L can be removed, for example, by a recess etch from above thetop surface of the second insulating cap layer 270. Each remainingportion of the dielectric core layer 62L constitutes a dielectric core62. Further, the horizontal portion of the second semiconductor channellayer 602 located above the top surface of the second insulating caplayer 270 can be removed by a planarization process, which can employ arecess etch or chemical mechanical planarization (CMP). Each remainingportion of the second semiconductor channel layer 602 can be locatedentirety within a memory opening 49 or entirely within a support opening(119, 219).

Each adjoining pair of a first semiconductor channel layer 601 and asecond semiconductor channel layer 602 can collectively form a verticalsemiconductor channel 60 through which electrical current can flow whena vertical NAND device including the vertical semiconductor channel 60is turned on. A tunneling dielectric layer 56 is surrounded by a chargestorage layer 54, and laterally surrounds a portion of the verticalsemiconductor channel 60. Each adjoining set of a blocking dielectriclayer 52, a charge storage layer 54, and a tunneling dielectric layer 56collectively constitute a memory film 50, which can store electricalcharges with a macroscopic retention time. In some embodiments, ablocking dielectric layer 52 may not be present in the memory film 50 atthis step, and a blocking dielectric layer may be subsequently formedafter formation of backside recesses. As used herein, a macroscopicretention time refers to a retention time suitable for operation of amemory device as a permanent memory device such as a retention time inexcess of 24 hours.

Referring to FIG. 9H, the top surface of each dielectric core 62 can befurther recessed within each memory opening, for example, by a recessetch to a depth that is located between the top surface of the secondinsulating cap layer 270 and the bottom surface of the second insulatingcap layer 270. Drain regions 63 can be formed by depositing a dopedsemiconductor material within each recessed region above the dielectriccores 62. The drain regions 63 can have a doping of a secondconductivity type that is the opposite of the first conductivity type.For example, if the first conductivity type is p-type, the secondconductivity type is n-type, and vice versa. The dopant concentration inthe drain regions 63 can be in a range from 5.0×10¹⁹/cm³ to2.0×10²¹/cm³, although lesser and greater dopant concentrations can alsobe employed. The doped semiconductor material can be, for example, dopedpolysilicon. Excess portions of the deposited semiconductor material canbe removed from above the top surface of the second insulating cap layer270, for example, by chemical mechanical planarization (CMP) or a recessetch to form the drain regions 63.

Each combination of a memory film 50 and a vertical semiconductorchannel 60 (which is a vertical semiconductor channel) within a memoryopening 49 constitutes a memory stack structure 55. The memory stackstructure 55 is a combination of a semiconductor channel, a tunnelingdielectric layer, a plurality of memory elements as embodied as portionsof the charge storage layer 54, and an optional blocking dielectriclayer 52. Each combination of a pedestal channel portion 11 (ifpresent), a memory stack structure 55, a dielectric core 62, and a drainregion 63 within a memory opening 49 constitutes a memory opening fillstructure 58. Each combination of a pedestal channel portion 11 (ifpresent), a memory film 50, a vertical semiconductor channel 60, adielectric core 62, and a drain region 63 within each support opening(119, 219) fills the respective support openings (119, 219), andconstitutes a support pillar structure 20.

The first-tier structure (132, 142, 170, 165), the second-tier structure(232, 242, 270, 265), the inter-tier dielectric layer 180, the memoryopening fill structures 58, and the support pillar structures 20collectively constitute a memory-level assembly. The memory-levelassembly is formed over the planar semiconductor material layer 10 suchthat the planar semiconductor material layer 10 includes horizontalsemiconductor channels electrically connected to vertical semiconductorchannels 60 within the memory stack structures 55.

Referring to FIGS. 10A and 10B, a first contact level dielectric layer280 can be formed over the memory-level assembly. The first contactlevel dielectric layer 280 is formed at a contact level through whichvarious contact via structures are subsequently formed to the drainregions 63 and the various electrically conductive layers that replacesthe sacrificial material layers (142, 242) in subsequent processingsteps.

Backside contact trenches 79 are subsequently formed through the firstcontact level dielectric layer 280 and the memory-level assembly. Forexample, a photoresist layer can be applied and lithographicallypatterned over the first contact level dielectric layer 280 to formelongated openings that extend along a first horizontal direction hdl.An anisotropic etch is performed to transfer the pattern in thepatterned photoresist layer through the first contact level dielectriclayer 280 and the memory-level assembly to a top surface of the planarsemiconductor material layer 10. The photoresist layer can besubsequently removed, for example, by ashing.

The backside contact trenches 79 extend along the first horizontaldirection hd1, and thus, are elongated along the first horizontaldirection hd1. The backside contact trenches 79 can be laterally spacedamong one another along a second horizontal direction hd2, which can beperpendicular to the first horizontal direction hd1. The backsidecontact trenches 79 can extend through the memory array region (e.g., amemory plane) 100 and the word line word line contact region 200. Thefirst subset of the backside contact trenches 79 laterally divides thememory-level assembly (e.g., into memory blocks).

Referring to FIGS. 11A and 11B, an etchant that selectively etches thematerials of the first and second sacrificial material layers (142, 242)with respect to the materials of the first and second insulating layers(132, 232), the first and second insulating cap layers (170, 270), andthe material of the outermost layer of the memory films 50 can beintroduced into the backside contact trenches 79, for example, employingan isotropic etch process. First backside recesses are formed in volumesfrom which the first sacrificial material layers 142 are removed. Secondbackside recesses are formed in volumes from which the secondsacrificial material layers 242 are removed. In one embodiment, thefirst and second sacrificial material layers (142, 242) can includesilicon nitride, and the materials of the first and second insulatinglayers (132, 232), can be silicon oxide. In another embodiment, thefirst and second sacrificial material layers (142, 242) can include asemiconductor material such as germanium or a silicon-germanium alloy,and the materials of the first and second insulating layers (132, 232)can be selected from silicon oxide and silicon nitride.

The isotropic etch process can be a wet etch process employing a wetetch solution, or can be a gas phase (dry) etch process in which theetchant is introduced in a vapor phase into the backside contact trench79. For example, if the first and second sacrificial material layers(142, 242) include silicon nitride, the etch process can be a wet etchprocess in which the exemplary structure is immersed within a wet etchtank including phosphoric acid, which etches silicon nitride selectiveto silicon oxide, silicon, and various other materials employed in theart. In case the sacrificial material layers (142, 242) comprise asemiconductor material, a wet etch process (which may employ a wetetchant such as a KOH solution) or a dry etch process (which may includegas phase HCl) may be employed.

Each of the first and second backside recesses can be a laterallyextending cavity having a lateral dimension that is greater than thevertical extent of the cavity. In other words, the lateral dimension ofeach of the first and second backside recesses can be greater than theheight of the respective backside recess. A plurality of first backsiderecesses can be formed in the volumes from which the material of thefirst sacrificial material layers 142 is removed. A plurality of secondbackside recesses can be formed in the volumes from which the materialof the second sacrificial material layers 242 is removed. Each of thefirst and second backside recesses can extend substantially parallel tothe top surface of the substrate 9. A backside recess can be verticallybounded by a top surface of an underlying insulating layer (132 or 232)and a bottom surface of an overlying insulating layer (132 or 232). Inone embodiment, each of the first and second backside recesses can havea uniform height throughout.

In one embodiment, a sidewall surface of each pedestal channel portion11 can be physically exposed at each bottommost first backside recessafter removal of the first and second sacrificial material layers (142,242). Further, a top surface of the planar semiconductor material layer10 can be physically exposed at the bottom of each backside contacttrench 79. An annular dielectric spacer (not shown) can be formed aroundeach pedestal channel portion 11 by oxidation of a physically exposedperipheral portion of the pedestal channel portions 11. Further, asemiconductor oxide potion (not shown) can be formed from eachphysically exposed surface portion of the planar semiconductor materiallayer 10 concurrently with formation of the annular dielectric spacers.

A backside blocking dielectric layer (not shown) can be optionallydeposited in the backside recesses and the backside contact trenches 79and over the first contact level dielectric layer 280. The backsideblocking dielectric layer can be deposited on the physically exposedportions of the outer surfaces of the memory stack structures 55. Thebackside blocking dielectric layer includes a dielectric material suchas a dielectric metal oxide, silicon oxide, or a combination thereof. Ifemployed, the backside blocking dielectric layer can be formed by aconformal deposition process such as atomic layer deposition or chemicalvapor deposition. The thickness of the backside blocking dielectriclayer can be in a range from 1 nm to 60 nm, although lesser and greaterthicknesses can also be employed.

At least one conductive material can be deposited in the plurality ofbackside recesses, on the sidewalls of the backside contact trench 79,and over the first contact level dielectric layer 280. The at least oneconductive material can include at least one metallic material, i.e., anelectrically conductive material that includes at least one metallicelement.

A plurality of first electrically conductive layers 146 can be formed inthe plurality of first backside recesses, a plurality of secondelectrically conductive layers 246 can be formed in the plurality ofsecond backside recesses, and a continuous metallic material layer (notshown) can be formed on the sidewalls of each backside contact trench 79and over the first contact level dielectric layer 280. Thus, the firstand second sacrificial material layers (142, 242) can be replaced withthe first and second conductive material layers (146, 246),respectively. Specifically, each first sacrificial material layer 142can be replaced with an optional portion of the backside blockingdielectric layer and a first electrically conductive layer 146, and eachsecond sacrificial material layer 242 can be replaced with an optionalportion of the backside blocking dielectric layer and a secondelectrically conductive layer 246. A backside cavity is present in theportion of each backside contact trench 79 that is not filled with thecontinuous metallic material layer.

The metallic material can be deposited by a conformal deposition method,which can be, for example, chemical vapor deposition (CVD), atomic layerdeposition (ALD), electroless plating, electroplating, or a combinationthereof. The metallic material can be an elemental metal, anintermetallic alloy of at least two elemental metals, a conductivenitride of at least one elemental metal, a conductive metal oxide, aconductive doped semiconductor material, a conductivemetal-semiconductor alloy such as a metal silicide, alloys thereof, andcombinations or stacks thereof. Non-limiting exemplary metallicmaterials that can be deposited in the backside recesses includetungsten, tungsten nitride, titanium, titanium nitride, tantalum,tantalum nitride, cobalt, and ruthenium. In one embodiment, the metallicmaterial can comprise a metal such as tungsten and/or metal nitride. Inone embodiment, the metallic material for filling the backside recessescan be a combination of titanium nitride layer and a tungsten fillmaterial. In one embodiment, the metallic material can be deposited bychemical vapor deposition or atomic layer deposition.

Residual conductive material can be removed from inside the backsidecontact trenches 79. Specifically, the deposited metallic material ofthe continuous metallic material layer can be etched back from thesidewalls of each backside contact trench 79 and from above the firstcontact level dielectric layer 280, for example, by an anisotropic orisotropic etch. Each remaining portion of the deposited metallicmaterial in the first backside recesses constitutes a first electricallyconductive layer 146. Each remaining portion of the deposited metallicmaterial in the second backside recesses constitutes a secondelectrically conductive layer 246. Each electrically conductive layer(146, 246) can be a conductive line structure.

A subset of the second electrically conductive layers 246 located at thelevels of the drain-select-level shallow trench isolation structures 72constitutes drain select gate electrodes. A subset of the firstelectrically conductive layers 146 located at each level of the annulardielectric spacers (not shown) constitutes source select gateelectrodes. A subset of the electrically conductive layer (146, 246)located between the drain select gate electrodes and the source selectgate electrodes can function as combinations of a control gate and aword line located at the same level. The control gate electrodes withineach electrically conductive layer (146, 246) are the control gateelectrodes for a vertical memory device including the memory stackstructure 55.

Each of the memory stack structures 55 comprises a vertical stack ofmemory elements located at each level of the electrically conductivelayers (146, 246). A subset of the electrically conductive layers (146,246) can comprise word lines for the memory elements. The semiconductordevices in the underlying peripheral device region 700 can comprise wordline switch devices configured to control a bias voltage to respectiveword lines. The memory-level assembly is located over the substratesemiconductor layer 9. The memory-level assembly includes at least onealternating stack (132, 146, 232, 246) and memory stack structures 55vertically extending through the at least one alternating stack (132,146, 232, 246). Each of the at least one an alternating stack (132, 146,232, 246) includes alternating layers of respective insulating layers(132 or 232) and respective electrically conductive layers (146 or 246).The at least one alternating stack (132, 146, 232, 246) comprisesstaircase regions that include terraces in which each underlyingelectrically conductive layer (146, 246) extends farther along the firsthorizontal direction hdl than any overlying electrically conductivelayer (146, 246) in the memory-level assembly.

Dopants of a second conductivity type, which is the opposite of thefirst conductivity type of the planar semiconductor material layer 10,can be implanted into a surface portion of the planar semiconductormaterial layer 10 to form a source region 61 underneath the bottomsurface of each backside contact trench 79. An insulating spacer 74including a dielectric material can be formed at the periphery of eachbackside contact trench 79, for example, by deposition of a conformalinsulating material (such as silicon oxide) and a subsequent anisotropicetch. The first contact level dielectric layer 280 may be thinned due toa collateral etch during the anisotropic etch that removes the verticalportions of horizontal portions of the deposited conformal insulatingmaterial.

A conformal insulating material layer can be deposited in the backsidecontact trenches 79, and can be anisotropically etched to forminsulating spacers 74. The insulating spacers 74 include an insulatingmaterial such as silicon oxide, silicon nitride, and/or a dielectricmetal oxide. A cavity laterally extending along the first horizontaldirection hdl is present within each insulating spacer 74.

A backside contact via structure can be formed in the remaining volumeof each backside contact trench 79, for example, by deposition of atleast one conductive material and removal of excess portions of thedeposited at least one conductive material from above a horizontal planeincluding the top surface of the first contact level dielectric layer280 by a planarization process such as chemical mechanical planarizationor a recess etch. The backside contact via structures are electricallyinsulated in all lateral directions, and is laterally elongated alongthe first horizontal direction hdl. As such, the backside contact viastructures are herein referred to as laterally-elongated contact viastructures 76. As used herein, a structure is “laterally elongated” ifthe maximum lateral dimension of the structure along a first horizontaldirection is greater than the maximum lateral dimension of the structurealong a second horizontal direction that is perpendicular to the firsthorizontal direction at least by a factor of 5.

Optionally, each laterally-elongated contact via structure 76 mayinclude multiple backside contact via portions such as a lower backsidecontact via portion and an upper backside contact via portion. In anillustrative example, the lower backside contact via portion can includea doped semiconductor material (such as doped polysilicon), and can beformed by depositing the doped semiconductor material layer to fill thebackside contact trenches 79 and removing the deposited dopedsemiconductor material from upper portions of the backside contacttrenches 79. The upper backside contact via portion can include at leastone metallic material (such as a combination of a TiN liner and a W fillmaterial), and can be formed by depositing the at least one metallicmaterial above the lower backside contact via portions, and removing anexcess portion of the at least one metallic material from above thehorizontal plane including the top surface of the first contact leveldielectric layer 280. The first contact level dielectric layer 280 canbe thinned and removed during a latter part of the planarizationprocess, which may employ chemical mechanical planarization (CMP), arecess etch, or a combination thereof. Each laterally-elongated contactvia structure 76 can be formed through the memory-level assembly and ona respective source region 61. The top surface of eachlaterally-elongated contact via structure 76 can located above ahorizontal plane including the top surfaces of the memory stackstructures 55.

Referring to FIGS. 12A and 12B, a second contact level dielectric layer282 can be optionally formed over the first contact level dielectriclayer 280. The second contact level dielectric layer 282 includes adielectric material such as silicon oxide or silicon nitride. Thethickness of the second contact level dielectric layer 282 can be in arange from 30 nm to 300 nm, although lesser and greater thicknesses canalso be employed.

Drain contact via structures 88 contacting the drain regions 63 canextend through the contact level dielectric layers (280, 282) and thesecond insulating cap layer 270 in the memory array region 100. A sourceconnection via structure 91 can extend through the contact leveldielectric layers (280, 282) to provide electrical connection to thelaterally-elongated contact via structures 76.

Various contact via structures can be formed through the contact leveldielectric layers (280, 282) and the retro-stepped dielectric materialportions (165, 265). For example, word line contact via structures 86can be formed in the word line word line contact region 200. A subset ofthe word line contact via structures 86 contacting the secondelectrically conductive layers 246 extends through the second-tierretro-stepped dielectric material portion 265 in the word line word linecontact region 200, and does not extend through the first-tierretro-stepped dielectric material portion 165. Another subset of theword line contact via structures 86 contacting the first electricallyconductive layers 146 extends through the second-tier retro-steppeddielectric material portion 265 and through the first-tier retro-steppeddielectric material portion 165 in the word line word line contactregion 200.

Referring to FIGS. 13A and 13B, a photoresist layer is applied over thesecond contact level dielectric layer 282, and is lithographicallypatterned to form openings in a peripheral region 400 located outsidethe memory array region 100 and the word line contact region 200. Forexample, the peripheral region 400 may surround memory array region 100and/or the word line contact region 200 and/or may be located on one ormore sides of the memory array region 100 and/or the word line contactregion 200. In one embodiment, the areas of the openings may be withinareas of openings in the planar semiconductor material layer 10 and theoptional planar conductive material layer 6.

Through-dielectric via cavities are formed by an anisotropic etchprocess that transfers the pattern of the openings in the photoresistlayer to the top surfaces of the topmost lower metal line structures788. Specifically, the through-dielectric via cavities can be formed inthe peripheral region 400 through the contact level dielectric layers(280, 282), the retro-stepped dielectric material portions (165, 265),the at least one second dielectric material layer 768, and the siliconnitride diffusion barrier layer 766 to a top surface of a respective oneof the topmost lower metal liner structures 788. In one embodiment, thethrough-dielectric via cavities can pass through openings in the planarsemiconductor material layer 10 and the optional planar conductivematerial layer 6. The photoresist layer can be removed, for example, byashing.

At least one conductive material can be simultaneously deposited in thethrough-dielectric via cavities. The at least one conductive materialcan include, for example, a metallic nitride liner (such as a TiN liner)and a metal fill material (such as W, Cu, Al, Ru, or Co). Excessportions of the at least one conductive material can be removed from thethrough-dielectric via cavities. For example, excess portions of the atleast one conductive material can be removed from above the top surfaceof the second contact level dielectric layer 282 by a planarizationprocess such as chemical mechanical planarization and/or a recess etch.Each remaining portion of the at least one conductive material in thethrough-dielectric via cavities that contacts a top surface of arespective one of the topmost lower metal line structure 788 constitutesa through-dielectric contact via structure 488.

Referring to FIG. 14, at least one upper interconnect level dielectriclayer 284 can be formed over the contact level dielectric layers (280,282). Various upper interconnect level metal structures can be formed inthe at least one upper interconnect level dielectric layer 284. Forexample, the various upper interconnect level metal structures caninclude line level metal interconnect structures (96, 98). The linelevel metal interconnect structures (96, 98) can include upper metalline structures 96 that contact a top surface of a respective one of thethrough-dielectric contact via structures 488, and bit lines 98 thatcontact a respective one of the drain contact via structures 88 andextend along the second horizontal direction (e.g., bit line direction)hd2 and perpendicular to the first horizontal direction (e.g., word linedirection) hdl. In one embodiment, a subset of the upper metal linestructures 96 may contact, or are electrically coupled to, a respectivepair of a word line contact via structure 86 and a through-dielectriccontact via structure 488.

Generally, memory stack structures 55 and an alternating stack (132,146, 232, 246) of insulating layers (132, 232) and electricallyconductive layers (146, 246) are formed over the silicon nitridediffusion barrier layer 766. The alternating stack (132, 146, 232, 246)includes stepped surfaces in which each electrically conductive layer(146, 246) other than a topmost electrically conductive layer laterallyextends farther than an overlying electrically conductive layer. Acontact level dielectric layer (280, 282) is formed over the alternatingstack (132, 146, 232, 246) and the memory stack structures 55. Word linecontact via structures 86 are formed on top surfaces of the electricallyconductive layers (146, 246).

At least a subset of the upper metal interconnect structures (whichinclude the line level metal interconnect structures (96, 98)) is formedover the three-dimensional memory array. A through-dielectric contactvia structure 488 can be provided through the retro-stepped dielectricmaterial portions (165, 265), the at least one second dielectricmaterial layer 768, and the silicon nitride diffusion barrier layer 766and directly on a top surface of another lower metal line structure(e.g., another topmost lower metal line structure 788) of the lowermetal interconnect structures 780. A line level dielectric layer 284 isformed over the contact level dielectric layer (280, 282). Bit lines 98which are electrically connected to a respective subset of the draincontact via structures 63 can be formed in the line level dielectriclayer 284.

In one embodiment, the three-dimensional memory device comprises amonolithic three-dimensional NAND memory device, the electricallyconductive layers (146, 246) comprise, or are electrically connected to,a respective word line of the monolithic three-dimensional NAND memorydevice, bottom ends of the memory stack structures 55 contact a planarsemiconductor material layer 10, and the monolithic three-dimensionalNAND memory device comprises an array of monolithic three-dimensionalNAND strings over the planar semiconductor material layer 10.

At least one memory cell in a first device level of the array ofmonolithic three-dimensional NAND strings is located over another memorycell in a second device level of the array of monolithicthree-dimensional NAND strings. The at least one semiconductor device710 comprises an integrated circuit comprising a driver circuit formonolithic three-dimensional NAND memory device located thereon. Theelectrically conductive layers (146, 246) comprise a plurality ofcontrol gate electrodes having a strip shape extending substantiallyparallel to the top surface of the substrate 9.

The plurality of control gate electrodes comprises at least a firstcontrol gate electrode located in the first device level and a secondcontrol gate electrode located in the second device level. The array ofmonolithic three-dimensional NAND strings comprises a plurality ofsemiconductor channels (59, 11, 60), wherein at least one end portion 60of each of the plurality of semiconductor channels (59, 11, 60) extendssubstantially perpendicular to a top surface of the semiconductorsubstrate, and a plurality of charge storage elements (as embodied asportions of the charge storage layers 54 located at levels of theelectrically conductive layers (146, 246)), each charge storage elementlocated adjacent to a respective one of the plurality of semiconductorchannels (59, 11, 60).

Referring to FIGS. 15A-15C, a stack including, from bottom to top, afirst (e.g., lower) silicon nitride layer 362 and a second (e.g., upper)silicon nitride layer 364 can be formed on the top surfaces of the bitlines 98 and the line level dielectric layer 284. Generally, the stackof the first and second silicon nitride layers (362, 364) can be formedat any level over the memory stack structures 55 and over the word linecontact via structures 86. In one embodiment, the stack of the first andsecond silicon nitride layers (362, 364) can be formed over the contactlevel dielectric layer(s) (280, 282). While the present disclosure isdescribed employing embodiments in which the stack of the first andsecond silicon nitride layers (362, 364) is formed on the top surfacesof the bit lines 98 and the line level dielectric layer 284, embodimentsare expressly contemplated herein in which the stack of the first andsecond silicon nitride layers (362, 364) is formed directly on a topsurface of the second insulating cap layer 270, the first contact leveldielectric layer 280, the second contact level dielectric layer 282, oranother dielectric material layer formed above the line level dielectriclayer 284.

The first silicon nitride layer 362 is formed as a “hydrogen-rich”silicon nitride layer, and the second silicon nitride layer 364 isformed as a “hydrogen-poor” silicon nitride layer which has a lowerhydrogen concentration than the first silicon nitride layer 362. In oneembodiment, the first silicon nitride layer 362 can include a firsthydrogen-to-nitrogen atomic ratio greater than 0.03, and the secondsilicon nitride layer includes a second hydrogen-to-nitrogen ratio lessthan 0.01. In one embodiment, the first hydrogen-to-nitrogen ratio canbe in a range from 0.03 to 0.08, such as from 0.04 to 0.06, and thesecond hydrogen-to-nitrogen ratio can be in a range from 0.001 to 0.01,such as from 0.002 to 0.006. In one embodiment, first silicon nitridelayer 362 has at least two times, such as two to four times, as muchhydrogen as the second silicon nitride layer 364.

In one embodiment, first silicon nitride layer 362 and the secondsilicon nitride layer 364 can be formed by plasma enhanced chemicalvapor deposition processes at a respective deposition temperature nothigher than 450 degrees Celsius with different gas flow conditions. Inone embodiment, each of the first and second silicon nitride layers(362, 364) can be deposited employing silane and ammonia as reactantgases and nitrogen gas as a carrier gas.

In one embodiment, the ratio of the ammonia flow rate to the silane flowrate during deposition of the first silicon nitride layer 362 can begreater than the ratio of the ammonia flow rate to the silane flow rateduring deposition of the second silicon nitride layer 364, such as formexample by a factor in a range from 1.25 to 2.5, such as from 1.4 to2.0. In one embodiment, a first RF power employed during deposition ofthe first silicon nitride layer 362 is greater than a second RF poweremployed during deposition of the second silicon nitride layer 364. Forexample, the ratio of the first RF power employed during deposition ofthe first silicon nitride layer 362 to the second RF power employedduring deposition of the second silicon nitride layer 364 can be in arange from 1.25 to 2.5, such as from 1.4 to 2.0.

In one embodiment, a pressure of the reaction chamber employed duringdeposition of the first silicon nitride layer 362 is greater than apressure of the reaction chamber employed during deposition of thesecond silicon nitride layer 364. For example, a ratio of the pressureof the reaction chamber employed during deposition of the first siliconnitride layer 362 to the pressure of the reaction chamber employedduring deposition of the second silicon nitride layer 364 can be in arange from 1.25 to 2.5, such as from 1.5 to 1.75. Nitrogen can beemployed as a carrier gas during deposition of the first and secondsilicon nitride layers (362, 364).

In a non-limiting illustrative example, the substrate 8 may be acommercially available 12″ diameter silicon substrate, and the exemplarystructure can include various material portion formed on the substrate 8as described above. In this case, deposition of the first siliconnitride layer 362 can be performed by placing the exemplary structure ofFIG. 14 into a plasma enhanced chemical vapor deposition (PECVD) chamberfor processing a 12″ semiconductor substrate, and by flowing a gasmixture of 15,000 to 20,000, such as 17,000 to 18,000 standard cubiccentimeters per minute (sccm) of nitrogen gas, 130 to 180, such as 150to 160 standard cubic centimeters per minute (sccm) of ammonia, and 250to 350 sscm, such as 275 to 300 standard cubic centimeters per minute ofsilane. The pressure of the process chamber can be maintained at about4.3 to 5 torr, such as 4.5 to 4.6 Torr. The spacing between theshowerhead and the 12″ substrate can be about 500 to 600 mils, forexample 550 to 560 mils, and the applied RF power can be about 800 to900 Watts, such as 825 to 850 Watts. In this case, the deposited siliconnitride film for the first silicon nitride layer 362 can have the firsthydrogen-to-nitrogen atomic ratio of about 0.048 to 0.053, such as 0.05and 0.051 as measured by Fourier transform infrared spectroscopy (FTIR)as a ratio a Si—H peak to a Si—N peak. Typical silicon nitride depositedby plasma enhanced chemical vapor deposition has a hydrogen-to-nitrogenatomic ratio of about 0.02.

In a non-limiting illustrative example, deposition of the second siliconnitride layer 364 can be performed by placing the exemplary structurewith the first silicon nitride layer 362 deposited thereupon into thesame process chamber, or into another plasma enhanced chemical vapordeposition (PECVD) chamber for processing a 12″ semiconductor substrate,and by flowing a gas mixture of 15,000 to 20,000, such as 17,000 to18,000 standard cubic centimeters per minute (sccm) of nitrogen gas, 130to 180, such as 150 to 160 standard cubic centimeters per minute (sccm)of ammonia, and 470 to 550, such as 490 to 510 standard cubiccentimeters per minute of silane. The pressure of the process chambercan be maintained at about 4 to 4.5 torr, such as 4.1 to 4.2 Torr. Thespacing between the showerhead and the 12″ substrate can be about 500 to600 mils, for example 550 to 560 mils, and the applied RF power can beabout 500 to 600 Watts, such as 525 to 550 Watts. In this case, thedeposited silicon nitride film for the second silicon nitride layer 364can have the second hydrogen-to-nitrogen atomic ratio of about 0.003 toabout 0.007, such as about 0.004 to about 0.005 as measured by Fouriertransform infrared spectroscopy (FTIR) as a ratio a Si—H peak to a Si—Npeak.

In one embodiment, the first silicon nitride layer has a first thicknessin a range from 10 nm to 500 nm, such as from 60 nm to 300 nm, althoughlesser and greater thicknesses can also be employed. The second siliconnitride layer has a second thickness in a range from 10 nm to 200 nm,such as from 30 nm to 100 nm, although lesser and greater thicknessescan also be employed.

Hydrogen atoms are present in the first silicon nitride layer 362 at ahigh atomic concentration as schematically illustrated in FIG. 15B. Forexample, the atomic concentration of hydrogen in the first siliconnitride layer 362 can be in a range from about 1.7% to about 4.6%(corresponding to the first hydrogen-to-nitrogen ratio from 0.03 to0.08), such as from about 2.3% to about 3.4% (corresponding to the firsthydrogen-to-nitrogen ratio from 0.04 to 0.06).

In one embodiment, the vertical semiconductor channels 60 can include,or can consist essentially of, undoped amorphous silicon, undopedpolysilicon, p-doped or n-doped amorphous silicon, p-doped or n-dopedpolysilicon, an undoped silicon-germanium alloy, or a p-doped or n-dopedsilicon-germanium alloy. In one embodiment, the vertical semiconductorchannels 60 can have an atomic concentration of silicon in a range from98% to 100%. In one embodiment, the vertical semiconductor channels 60can include, or consist essentially of, undoped polysilicon, p-dopedpolysilicon, or n-doped polysilicon. The silicon atoms in the verticalsemiconductor channels 60 can have dangling bonds (DB) at grainboundaries as illustrated in FIG. 15C.

Referring to FIGS. 16A-16D, an anneal process can be performed at anelevated temperature. The anneal process can induce formation ofhydrogen bonds within the semiconductor material in the verticalsemiconductor channels 60 by diffusing hydrogen atoms from the firstsilicon nitride layer 362 into the vertical semiconductor channels 60.The second silicon nitride layer 364 includes hydrogen atoms at a lowatomic concentration, and thus, does not provide hydrogen diffusionpaths therethrough. Thus, the second silicon nitride layer 364 blocksdiffusion of hydrogen atom therethrough during the anneal process. Incontrast, the first silicon nitride layer 362 includes hydrogen at highatomic concentration, and thus, functions as a hydrogen supply sourceduring the anneal process. Further, the high concentration of hydrogenatoms in the first silicon nitride layer provides porous paths throughwhich hydrogen atoms can diffuse into the underlying dielectric materiallayers such as the line level dielectric layer 284 and the first andsecond contact level dielectric layers (280, 282). The hydrogen atomsthat diffuse to the first contact level dielectric layer 280 can diffuseinto the vertical semiconductor channels 60 through top surfaces of thevertical semiconductor channels 60 or through the alternating stacks(132, 146, 232, 246) and through the memory films 50. Exemplary hydrogendiffusion paths HDP are illustrated in FIGS. 16A, 16B, and 16C.

The elevated temperature of the anneal process and the duration of theanneal process can be selected to provide sufficient hydrogen diffusionout of the first silicon nitride layer 362 into the verticalsemiconductor channels 60. In one embodiment, the elevated temperaturecan be in a range from 300 degrees Celsius to 800 degrees Celsius. Inone embodiment, the elevated temperature can be maintained for aduration in a range from 10 seconds to 24 hours, such as from 1 minuteto 1 hour, during the anneal process.

In one embodiment, duration of the anneal process and the elevatedtemperature can be selected such that the ratio of the total number ofdangling bonds DB in the vertical semiconductor channels 60 to the totalnumber of hydrogen bonds (illustrated in FIG. 16D) in the verticalsemiconductor channels 60 can be in a range from 0 to 0.25 after theanneal process. In other words, at least 80% all dangling bonds DB inthe vertical semiconductor channels 60 can be converted into hydrogenbonds by the anneal process. In one embodiment, the anneal process maybe employed as an activation anneal process that activates the dopantatoms in the source regions 61, in the vertical semiconductor channels60, and in the drain regions 63.

In one embodiment, the vertical semiconductor channels 60 can comprise,and/or can consist essentially of, polysilicon. The atomic concentrationof silicon in the polysilicon material of the vertical semiconductorchannels 60 can be in a range from 98% to 99.999999%, such as from 99%to 99.9999% after the anneal process. The balance percentage isprimarily attributable to p-type dopant atoms or n-type dopant atoms,and hydrogen atoms in the hydrogen bonds.

The silicon nitride diffusion barrier layer 766 can function as ahydrogen-blocking layer during the anneal process. Thus, the hydrogenatoms can be trapped between the silicon nitride diffusion barrier layer766 and the second silicon nitride layer 364 during the anneal process.In one embodiment, the silicon nitride diffusion barrier layer 766 canhave a hydrogen-to-nitrogen ratio less than 0.01 prior to, and after,the anneal process.

Referring to FIG. 17, the first and second silicon nitride layers (362,364) can be removed selective to the line level dielectric layer 284 andthe upper metal interconnect structures (96, 98) embedded therein. Inone embodiment, the first and second silicon nitride layers (362, 364)can be removed by a single etch process. In an illustrative example, awet etch process employing hot phosphoric acid can be employed to removethe first and second silicon nitride layers (362, 264).

Referring to FIG. 18, at least one interconnect level dielectric layer290 embedding additional metal interconnect structures (292, 294, 296,298) can be formed over the over the vertical semiconductor channels 60after removal of the first and second silicon nitride layers (362, 364).The additional metal interconnect structures (292, 294, 296, 298) can beformed in the at least one interconnect level dielectric layer 290 levelby level. The additional metal interconnect structures (292, 294, 296,298) can include metal via structures (292, 296) and metal linestructures (294, 298). While two levels of metal via structures (292,296) and two levels of metal line structures (204, 298) are illustratedherein, it is understood that as many levels of metal via structures(292, 296) and as many levels of metal line structures (294, 298) can beformed. Each layer within the at least one interconnect level dielectriclayer 290 includes a dielectric material such as undoped silicate glass,doped silicate glass, or organosilicate glass. In one embodiment, asubset of the additional metal interconnect structures (292, 294, 296,298) can be electrically shorted to an upper end of a respective one ofthe vertical semiconductor channels 60.

In one embodiment, a passivation silicon nitride layer 368 can be formedover the at least one interconnect level dielectric layer 290. Thepassivation silicon nitride layer 368 can be a diffusion barrier layerfor hydrogen atoms. The atomic concentration of hydrogen atoms in thepassivation silicon nitride layer 368 can be less than 0.5%, and thethickness of the passivation silicon nitride layer 368 can be in a rangefrom 50 nm to 500 nm, although lesser and greater thicknesses can alsobe employed.

The processing temperature of all processes after removal of the firstand second silicon nitride layers (362, 364) can be maintained below 600degrees, and preferably below 500 degrees to minimize loss of hydrogenatoms from the vertical semiconductor channels 60. Formation of thepassivation silicon nitride layer 368 can trap the hydrogen atoms in thevertical semiconductor channels 60 between the silicon nitride barrierlayer 766 and the passivation silicon nitride layer 368, therebyminimizing loss of hydrogen passivation during operation of thesemiconductor devices.

Hydrogen passivation of the vertical semiconductor channels 60 canincrease the cell current, i.e., the electrical current through eachvertical semiconductor channel 60, by a percentage in a range from 1% to10%, such as from 2% to 8%. The increase in the cell current can beadvantageously employed to provide faster device performance and/orincreases sense margin.

The methods of the present disclosure provide a high degree of hydrogenpassivation in the vertical semiconductor channels 60 by employing anon-substrate structure, i.e., the first silicon nitride layer 362, as ahydrogen source. By providing the hydrogen source in proximity to thememory stack structures 55 prior to formation of the additional metalinterconnect structures (292, 294, 296, 298), the efficiency of hydrogenpassivation during the anneal process can be enhanced. By removing thefirst and second silicon nitride layers (362, 364) prior to formation ofthe metal interconnect structures (292, 294, 296, 298), capacitanceincrease due to presence of a silicon nitride material is avoided. Themethods of the present disclosure can increase the cell current ofvertical field effect transistors without the adverse impact ofintroducing a high dielectric constant material such as a silicondielectric layer in signal paths within the interconnect dielectriclayers.

Although the foregoing refers to particular embodiments, it will beunderstood that the disclosure is not so limited. It will occur to thoseof ordinary skill in the art that various modifications may be made tothe disclosed embodiments and that such modifications are intended to bewithin the scope of the disclosure. Compatibility is presumed among allembodiments that are not alternatives of one another. The word“comprise” or “include” contemplates all embodiments in which the word“consist essentially of” or the word “consists of” replaces the word“comprise” or “include,” unless explicitly stated otherwise. Where anembodiment employing a particular structure and/or configuration isillustrated in the present disclosure, it is understood that the presentdisclosure may be practiced with any other compatible structures and/orconfigurations that are functionally equivalent provided that suchsubstitutions are not explicitly forbidden or otherwise known to beimpossible to one of ordinary skill in the art. All of the publications,patent applications and patents cited herein are incorporated herein byreference in their entirety.

1. A method of forming a three-dimensional memory device, comprising:forming memory stack structures vertically extending through analternating stack of insulating layers and electrically conductivelayers over a substrate, wherein each of the memory stack structurescomprises a memory film and a vertical semiconductor channel laterallysurrounded by the memory film; forming a stack including, from bottom totop, a first silicon nitride layer and a second silicon nitride layerover the memory stack structures, wherein the first silicon nitridelayer has a higher hydrogen-to-nitrogen ratio than the second siliconnitride layer; performing an anneal process to diffuse hydrogen from thefirst silicon nitride layer into the memory stack structures; andremoving the first and second silicon nitride layers.
 2. The method ofclaim 1, wherein: the semiconductor channels of the memory stackstructures comprise polysilicon channels having dangling bonds; and theanneal process passivates the dangling bonds in the polysilicon channelsby diffusing the hydrogen from the first silicon nitride layer into thepolysilicon channels while the second silicon nitride layer blocksdiffusion of hydrogen therethrough.
 3. The method of claim 1, whereinthe first silicon nitride layer includes a first hydrogen-to-nitrogenatomic ratio greater than 0.03, and the second silicon nitride layerincludes a second hydrogen-to-nitrogen ratio less than 0.01.
 4. Themethod of claim 3, wherein the first silicon nitride layer and thesecond silicon nitride layer are formed by plasma enhanced chemicalvapor deposition processes at a respective deposition temperature nothigher than 450 degrees Celsius with different gas flow conditions. 5.The method of claim 4, wherein each of the first and second siliconnitride layers is deposited employing silane and ammonia as reactantgases and nitrogen gas as a carrier gas.
 6. The method of claim 5,wherein a ratio of an ammonia flow rate to a silane flow rate duringdeposition of the first silicon nitride layer is greater than a ratio ofan ammonia flow rate to a silane flow rate during deposition of thesecond silicon nitride layer by a factor in a range from 1.25 to 2.5. 7.The method of claim 5, wherein a ratio of a first RF power employedduring deposition of the first silicon nitride layer to a second RFpower employed during deposition of the second silicon nitride layer isin a range from 1.25 to 2.5.
 8. The method of claim 1, furthercomprising: forming drain regions at upper ends of the verticalsemiconductor channels; forming a contact level dielectric layer overthe drain regions; forming drain contact via structures through thecontact level dielectric layer on the drain regions, wherein the firstand second silicon nitride layers are formed over the contact leveldielectric layer.
 9. The method of claim 8, further comprising: forminga line level dielectric layer over the contact level dielectric layer;and forming bit lines electrically connected to a respective subset ofthe drain contact via structures in the line level dielectric layer,wherein the first silicon nitride layer is formed on top surfaces of thebit lines and the line level dielectric layer.
 10. The method of claim1, wherein: the elevated temperature is in a range from 300 degreesCelsius to 800 degrees Celsius; the elevated temperature is maintainedfor a duration in a range from 10 seconds to 24 hours during the annealprocess; the first silicon nitride layer has a first thickness in arange from 10 nm to 500 nm; and the second silicon nitride layer has asecond thickness in a range from 10 nm to 200 nm.
 11. The method ofclaim 1, wherein the first and second silicon nitride layers are removedby a single etch process.
 12. The method of claim 11, wherein the firstand second silicon nitride layers are removed by a wet etch processemploying hot phosphoric acid.
 13. The method of claim 1, furthercomprising: forming at least one interconnect level dielectric layerover the vertical semiconductor channels after removal of the first andsecond silicon nitride layers; forming metal interconnect structures inthe at least one interconnect level dielectric layer, wherein a subsetof the metal interconnect structures is electrically shorted to an upperend of a respective one of the vertical semiconductor channels; andforming a passivation silicon nitride layer over the at least oneinterconnect level dielectric layer, wherein the passivation siliconnitride layer is a diffusion barrier layer for hydrogen atoms.
 14. Themethod of claim 2, wherein duration of the anneal process and theelevated temperature are selected such that a ratio of a total number ofthe dangling bonds in the vertical semiconductor channels to a totalnumber of hydrogen bonds in the vertical semiconductor channels is in arange from 0 to 0.25 after the anneal process.
 15. The method of claim2, wherein the vertical semiconductor channel comprises polysilicon withan atomic concentration of silicon in a range from 98% to 99.999999%after the anneal process.
 16. The method of claim 3, wherein: the firsthydrogen-to-nitrogen ratio is in a range from 0.03 to 0.08; and thesecond hydrogen-to-nitrogen ratio is in a range from 0.001 to 0.01. 17.The method of claim 1, further comprising: forming semiconductor deviceson a top surface of the substrate; forming lower interconnect leveldielectric layers embedding lower metal interconnect structures thereinover the semiconductor devices, wherein the lower metal interconnectstructures are electrically connected to a respective one of thesemiconductor devices; and forming a silicon nitride diffusion barrierlayer over the lower interconnect level dielectric layer, wherein: thememory stack structures and the alternating stack of insulating layersand electrically conductive layers are formed over the silicon nitridediffusion barrier layer; and the silicon nitride diffusion barrier layerblocks diffusion of hydrogen atoms therethrough during the annealprocess.
 18. The method of claim 17, wherein the silicon nitridediffusion barrier layer has a hydrogen-to-nitrogen ratio less than 0.01prior to, and after, the anneal process.
 19. The method of claim 1,wherein: the alternating stack includes stepped surfaces in which eachelectrically conductive layer other than a topmost electricallyconductive layer laterally extends farther than an overlyingelectrically conductive layer; the method further comprises formingcontact via structures on top surfaces of the electrically conductivelayers; and the first and second silicon nitride layers are formed overthe contact via structures.
 20. The method of claim 1, wherein: thethree-dimensional memory device comprises a monolithic three-dimensionalNAND memory device; the electrically conductive layers comprise, or areelectrically connected to, a respective word line of the monolithicthree-dimensional NAND memory device; the substrate comprises a siliconsubstrate; the monolithic three-dimensional NAND memory device comprisesan array of monolithic three-dimensional NAND strings formed over thesilicon substrate; at least one memory cell in a first device level ofthe array of monolithic three-dimensional NAND strings is located overanother memory cell in a second device level of the array of monolithicthree-dimensional NAND strings; the silicon substrate contains anintegrated circuit comprising a driver circuit for the array ofmonolithic three-dimensional NAND strings; the electrically conductivelayers comprise a plurality of control gate electrodes having a stripshape extending substantially parallel to the top surface of thesubstrate, the plurality of control gate electrodes comprise at least afirst control gate electrode located in the first device level and asecond control gate electrode located in the second device level; andthe array of monolithic three-dimensional NAND strings comprises: aplurality of semiconductor channels, wherein at least one end portion ofeach of the plurality of semiconductor channels extends substantiallyperpendicular to a top surface of the substrate, and a plurality ofcharge storage elements, each charge storage element located adjacent toa respective one of the plurality of semiconductor channels.